HFCC-01 Low-Level Software (LLSW) Rel_6802_HFCC-01-RP-CSAR-CB
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analogIn.h
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1/*
2 * Copyright (c) 2025, TUSAS Malaysia
3 * All rights reserved.
4 * This file contains proprietary information. This
5 * file shall not be duplicated, used, modified,
6 * or disclosed in whole or in part without
7 * the express written consent of TUSAS.
8 */
9
18
19#ifndef INCLUDED_ANALOG_IN_H
20#define INCLUDED_ANALOG_IN_H
21
22#include "commonDataTypes.h"
23#include "driverStatus.h"
24
28typedef enum
29{
34
59
74
89
99
124
139
154
164
168typedef struct
169{
170 UInt32 baseAddress;
172
202 AnalogInPbitStatus *pbitStatus);
203
233 AnalogInCbitStatus *cbitStatus);
234
264DriverStatus analogIn_getTemp(const AnalogInDevHandler analogInDevHdl, Float32 *temp5v,
265 Float32 *temp10v);
266
295DriverStatus analogIn_enableDisableCh(const AnalogInDevHandler analogInDevHdl, const UInt8 chNum,
296 const Bool flag);
297
326DriverStatus analogIn_getInputRange(const AnalogInDevHandler analogInDevHdl, const UInt8 bank,
327 UInt32 *range);
328
357DriverStatus analogIn_getAdcReading(const AnalogInDevHandler analogInDevHdl, const UInt8 chNum,
358 Float32 *adcValue);
359
388DriverStatus analogIn_getChannelStatus(const AnalogInDevHandler analogInDevHdl, const UInt8 chNum,
389 Bool *status);
390
391#endif // INCLUDED_ANALOG_IN_H
DriverStatus analogIn_getInputRange(const AnalogInDevHandler analogInDevHdl, const UInt8 bank, UInt32 *range)
analogIn_getInputRange.
Definition analogIn.c:268
AInBITState
Analog Input Built-In Test (BIT) Pass/Fail Evaluation State.
Definition analogIn.h:29
@ AIN_BIT_PASS
Analog Input BIT for NO ERROR condition is 0.
Definition analogIn.h:30
@ AIN_BIT_FAIL
Analog Input BIT for ERROR condition is 1.
Definition analogIn.h:31
DriverStatus analogIn_getPbit(const AnalogInDevHandler analogInDevHdl, AnalogInPbitStatus *pbitStatus)
analogIn_getPbit.
Definition analogIn.c:32
DriverStatus analogIn_getCbit(const AnalogInDevHandler analogInDevHdl, AnalogInCbitStatus *cbitStatus)
analogIn_getCbit.
Definition analogIn.c:119
DriverStatus analogIn_getAdcReading(const AnalogInDevHandler analogInDevHdl, const UInt8 chNum, Float32 *adcValue)
analogIn_getAdcReading.
Definition analogIn.c:288
DriverStatus analogIn_getChannelStatus(const AnalogInDevHandler analogInDevHdl, const UInt8 chNum, Bool *status)
analogIn_getChannelStatus.
Definition analogIn.c:311
DriverStatus analogIn_enableDisableCh(const AnalogInDevHandler analogInDevHdl, const UInt8 chNum, const Bool flag)
analogIn_enableDisableCh.
Definition analogIn.c:238
DriverStatus analogIn_getTemp(const AnalogInDevHandler analogInDevHdl, Float32 *temp5v, Float32 *temp10v)
analogIn_getTemp.
Definition analogIn.c:206
DriverStatus
Low-Level Device Driver Execution Status and Return Error Codes.
Definition driverStatus.h:24
Analog Input Continuous Built-In Test (CBIT) Composite Diagnostic Status Structure.
Definition analogIn.h:159
CbitIvr cbitIvrErrorStatus
AIN CBIT IVR error status.
Definition analogIn.h:162
CbitStat cbitStatus
AIN CBIT status.
Definition analogIn.h:160
CbitOverVoltage cbitOverVoltage
AIN CBIT over voltage.
Definition analogIn.h:161
Analog Input (ADC) Peripheral Hardware Device Handler Structure.
Definition analogIn.h:169
UInt32 baseAddress
Device base memory address.
Definition analogIn.h:170
Analog Input Power-On Built-In Test (PBIT) Composite Diagnostic Status Structure.
Definition analogIn.h:94
PbitOverVoltage pbitOverVoltage
AIN PBit over voltage status.
Definition analogIn.h:96
PbitIvr pbitIvrErrorStatus
AIN PBit IVR error status.
Definition analogIn.h:97
PbitStat pbitStatus
AIN PBit status.
Definition analogIn.h:95
Analog Input Continuous Built-In Test (CBIT) Input Voltage Range (IVR) Fault Status Structure.
Definition analogIn.h:144
AInBITState cbitIvrErrCh6
AIN CBIT condition for ivr error Channel 6.
Definition analogIn.h:150
AInBITState cbitIvrErrCh7
AIN CBIT condition for ivr error Channel 7.
Definition analogIn.h:151
AInBITState cbitIvrErrCh5
AIN CBIT condition for ivr error Channel 5.
Definition analogIn.h:149
AInBITState cbitIvrErrCh4
AIN CBIT condition for ivr error Channel 4.
Definition analogIn.h:148
AInBITState cbitIvrErrCh1
AIN CBIT condition for ivr error Channel 1.
Definition analogIn.h:145
AInBITState cbitIvrErrCh2
AIN CBIT condition for ivr error Channel 2.
Definition analogIn.h:146
AInBITState cbitIvrErrCh8
AIN CBIT condition for ivr error Channel 8.
Definition analogIn.h:152
AInBITState cbitIvrErrCh3
AIN CBIT condition for ivr error Channel 3.
Definition analogIn.h:147
Analog Input Continuous Built-In Test (CBIT) Over-Voltage Fault Status Structure.
Definition analogIn.h:129
AInBITState cbitOvpCh7
AIN CBIT condition for over voltage protection Channel 7.
Definition analogIn.h:136
AInBITState cbitOvpCh4
AIN CBIT condition for over voltage protection Channel 4.
Definition analogIn.h:133
AInBITState cbitOvpCh2
AIN CBIT condition for over voltage protection Channel 2.
Definition analogIn.h:131
AInBITState cbitOvpCh3
AIN CBIT condition for over voltage protection Channel 3.
Definition analogIn.h:132
AInBITState cbitOvpCh8
AIN CBIT condition for over voltage protection Channel 8.
Definition analogIn.h:137
AInBITState cbitOvpCh1
AIN CBIT condition for over voltage protection Channel 1.
Definition analogIn.h:130
AInBITState cbitOvpCh5
AIN CBIT condition for over voltage protection Channel 5.
Definition analogIn.h:134
AInBITState cbitOvpCh6
AIN CBIT condition for over voltage protection Channel 6.
Definition analogIn.h:135
Analog Input Continuous Built-In Test (CBIT) General Status Flags Structure.
Definition analogIn.h:104
AInBITState cbitFault5v
AIN CBIT 5.0V fault status.
Definition analogIn.h:107
AInBITState cbitIcCommErrCh1
AIN CBIT Channel 1 communication error status.
Definition analogIn.h:113
AInBITState cbitFault3v3
AIN CBIT 3.3V fault status.
Definition analogIn.h:106
AInBITState cbitIcCommErrLbBank0
AIN CBIT Bank 0 communication error status.
Definition analogIn.h:121
AInBITState cbitFault15v
AIN CBIT 15.0V fault status.
Definition analogIn.h:108
AInBITState cbitIcCommErrCh5
AIN CBIT Channel 5 communication error status.
Definition analogIn.h:117
AInBITState cbitIcCommErrCh6
AIN CBIT Channel 6 communication error status.
Definition analogIn.h:118
AInBITState cbitIcCommErrLbBank1
AIN CBIT Bank 1 communication error status.
Definition analogIn.h:122
AInBITState cbitIcCommErrCh3
AIN CBIT Channel 3 communication error status.
Definition analogIn.h:115
AInBITState cbitOtBank1
AIN CBIT Bank 1 over temperature status.
Definition analogIn.h:112
AInBITState cbitUtBank1
AIN CBIT Bank 1 under temperature status.
Definition analogIn.h:111
AInBITState notRun
AIN CBIT not run status.
Definition analogIn.h:105
AInBITState cbitUtBank0
AIN CBIT Bank 0 under temperature status.
Definition analogIn.h:109
AInBITState cbitIcCommErrCh4
AIN CBIT Channel 4 communication error status.
Definition analogIn.h:116
AInBITState cbitIcCommErrCh8
AIN CBIT Channel 8 communication error status.
Definition analogIn.h:120
AInBITState cbitIcCommErrCh2
AIN CBIT Channel 2 communication error status.
Definition analogIn.h:114
AInBITState cbitOtBank0
AIN CBIT Bank 0 over temperature status.
Definition analogIn.h:110
AInBITState cbitIcCommErrCh7
AIN CBIT Channel 7 communication error status.
Definition analogIn.h:119
Analog Input Power-On Built-In Test (PBIT) Input Voltage Range (IVR) Fault Status Structure.
Definition analogIn.h:79
AInBITState pbitIvrErrCh5
AIN PBIT condition for ivr error Channel 5.
Definition analogIn.h:84
AInBITState pbitIvrErrCh7
AIN PBIT condition for ivr error Channel 7.
Definition analogIn.h:86
AInBITState pbitIvrErrCh1
AIN PBIT condition for ivr error Channel 1.
Definition analogIn.h:80
AInBITState pbitIvrErrCh3
AIN PBIT condition for ivr error Channel 3.
Definition analogIn.h:82
AInBITState pbitIvrErrCh4
AIN PBIT condition for ivr error Channel 4.
Definition analogIn.h:83
AInBITState pbitIvrErrCh2
AIN PBIT condition for ivr error Channel 2.
Definition analogIn.h:81
AInBITState pbitIvrErrCh6
AIN PBIT condition for ivr error Channel 6.
Definition analogIn.h:85
AInBITState pbitIvrErrCh8
AIN PBIT condition for ivr error Channel 8.
Definition analogIn.h:87
Analog Input Power-On Built-In Test (PBIT) Over-Voltage Fault Status Structure.
Definition analogIn.h:64
AInBITState pbitOvpCh2
AIN PBIT condition for over voltage protection Channel 2.
Definition analogIn.h:66
AInBITState pbitOvpCh7
AIN PBIT condition for over voltage protection Channel 7.
Definition analogIn.h:71
AInBITState pbitOvpCh6
AIN PBIT condition for over voltage protection Channel 6.
Definition analogIn.h:70
AInBITState pbitOvpCh4
AIN PBIT condition for over voltage protection Channel 4.
Definition analogIn.h:68
AInBITState pbitOvpCh1
AIN PBIT condition for over voltage protection Channel 1.
Definition analogIn.h:65
AInBITState pbitOvpCh5
AIN PBIT condition for over voltage protection Channel 5.
Definition analogIn.h:69
AInBITState pbitOvpCh3
AIN PBIT condition for over voltage protection Channel 3.
Definition analogIn.h:67
AInBITState pbitOvpCh8
AIN PBIT condition for over voltage protection Channel 8.
Definition analogIn.h:72
Analog Input Power-On Built-In Test (PBIT) General Status Flags Structure.
Definition analogIn.h:39
AInBITState pbitFault5v
AIN PBIT 5.0V fault status.
Definition analogIn.h:42
AInBITState pbitOtBank0
AIN PBIT Bank 0 over temperature status.
Definition analogIn.h:45
AInBITState pbitUtBank1
AIN PBIT Bank 1 under temperature status.
Definition analogIn.h:46
AInBITState pbitIcCommErrLbBank1
AIN PBIT Bank 1 communication error status.
Definition analogIn.h:57
AInBITState pbitIcCommErrCh3
AIN PBIT Channel 3 communication error status.
Definition analogIn.h:50
AInBITState pbitOtBank1
AIN PBIT Bank 1 over temperature status.
Definition analogIn.h:47
AInBITState pbitIcCommErrCh4
AIN PBIT Channel 4 communication error status.
Definition analogIn.h:51
AInBITState pbitIcCommErrCh8
AIN PBIT Channel 8 communication error status.
Definition analogIn.h:55
AInBITState pbitIcCommErrCh5
AIN PBIT Channel 5 communication error status.
Definition analogIn.h:52
AInBITState incompleted
AIN PBIT incomplete status.
Definition analogIn.h:40
AInBITState pbitIcCommErrCh7
AIN PBIT Channel 7 communication error status.
Definition analogIn.h:54
AInBITState pbitIcCommErrLbBank0
AIN PBIT Bank 0 communication error status.
Definition analogIn.h:56
AInBITState pbitFault15v
AIN PBIT 15.0V fault status.
Definition analogIn.h:43
AInBITState pbitUtBank0
AIN PBIT Bank 0 under temperature status.
Definition analogIn.h:44
AInBITState pbitIcCommErrCh2
AIN PBIT Channel 2 communication error status.
Definition analogIn.h:49
AInBITState pbitIcCommErrCh1
AIN PBIT Channel 1 communication error status.
Definition analogIn.h:48
AInBITState pbitFault3v3
AIN PBIT 3.3V fault status.
Definition analogIn.h:41
AInBITState pbitIcCommErrCh6
AIN PBIT Channel 6 communication error status.
Definition analogIn.h:53