core.h

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/*
 * Copyright (c) 2025, TUSAS Malaysia
 * All rights reserved. 
 * This file contains proprietary information. This
 * file shall not be duplicated, used, modified,
 * or disclosed in whole or in part without
 * the express written consent of TUSAS.
 */

 
#ifndef INCLUDED_CORE_H
#define INCLUDED_CORE_H
 
#include "commonDataTypes.h"
#include "driverStatus.h"
#include "interDrv.h"
 
#define CORE_MFB1_INDEX (0U)
#define CORE_MFB2_INDEX (1U)
 
#define CORE_LED_COLOR_RED    (1U)
#define CORE_LED_COLOR_GREEN  (2U)
#define CORE_LED_COLOR_YELLOW (3U)
#define CORE_LED_COLOR_OFF    (4U)
 
#define CORE_MAX_MIO_FUNC (5U)
#define CORE_MAX_MIO_CHAR (4U)

typedef enum
{
   MFB_READY = 0, 
   MFB_NOT_READY = 1 
} MfbReadyStatus;

typedef enum
{
   PF_OK = 1U, 
   PF_FAULT = 0U 
} PowerFailState;

typedef struct
{
   UInt32 serialNum; 
   Char platform[CORE_MAX_MIO_CHAR]; 
   Char model[CORE_MAX_MIO_CHAR]; 
   Char generation[CORE_MAX_MIO_CHAR]; 
   Char mainBrdRev[CORE_MAX_MIO_CHAR]; 
   UInt32 fpgaFirmVer; 
   UInt32 cpldFirmVer; 
   UInt32 mioSlotCount; 
   UInt32 mioStartAddr[CORE_MAX_MIO_FUNC]; 
   UInt32 mioAddrSize[CORE_MAX_MIO_FUNC]; 
   Char mioID[CORE_MAX_MIO_FUNC][CORE_MAX_MIO_CHAR]; 
} CardDetails;

typedef struct
{
   UInt32 pbitStatus; 
   UInt32 cbitStatus; 
   Float32 coreTemp; 
   Float32 dramTemp; 
   Float32 fpgaTemp; 
   Float32 efuseTemp; 
   Float32 dcdcTemp; 
} CardStatus;

DriverStatus core_register(const IODevice gpIODev4, const MemoryRegion nvsramMR);

DriverStatus core_mfbIoInit(void);

DriverStatus core_getMfbReadyStatus(const UInt8 mfbIndex, MfbReadyStatus *mfbStatusPtr);

DriverStatus core_statusLEDInit(void);

DriverStatus core_statusLEDSet(const UInt32 color);

DriverStatus core_statusPwrFailInit(void);

DriverStatus core_statusPwrFailGet(PowerFailState *pwrFailStatusPtr);

DriverStatus core_cardInfo(const UInt32 baseAddr, CardDetails *cardDetailsPtr);

DriverStatus core_cardStatus(const UInt32 baseAddr, CardStatus *cardStatusPtr);

DriverStatus core_nvsramRead32(void *const buff, const UInt32 offset);

DriverStatus core_nvsramWrite32(void const *buff, const UInt32 offset);

DriverStatus core_getMemoryRegion(RegionInfo *region);

DriverStatus core_enableDisableHeartbeat(const UInt32 baseAddress, const Bool state);

DriverStatus core_getHeartbeatResolution(const UInt32 baseAddress, UInt32 *resolution);

DriverStatus core_setHeartbeatTimeoutCount(const UInt32 baseAddress, const UInt32 count);

DriverStatus core_getHeartbeatElapsedCount(const UInt32 baseAddress, UInt32 *count);

DriverStatus core_feedHeartbeat(const UInt32 baseAddress, const UInt32 feedingValue);
 
#endif // INCLUDED_CORE_H