core_nvsram_map_8h_source.html

/*

 * Copyright (c) 2025, TUSAS Malaysia

 * All rights reserved.

 * This file contains proprietary information. This

 * file shall not be duplicated, used, modified,

 * or disclosed in whole or in part without

 * the express written consent of TUSAS.

 */


#ifndef INCLUDED_CORE_NVSRAM_MAP_H

#define INCLUDED_CORE_NVSRAM_MAP_H


#include "nvsram.h"


// NVSRAM Device ID

#define CORE_NVSRAM_ID NVSRAM_DEV_0


#define CORE_NVSRAM_INVALID_ID (0xFFU)


// NVSRAM Memory Size

#define CORE_NVSRAM_MEMORY_SIZE (0x1000U)


// Offset for Built-In Test

#define CORE_NVSRAM_OFFSET_BITS (0x00000000U)


// Maximum number of offset Power Fail

#define CORE_NVSRAM_OFFSET_MAX_PWR_FAIL (1U)


// Maximum number of offset PBITs

#define CORE_NVSRAM_OFFSET_MAX_AIN_PBIT   (2U)

#define CORE_NVSRAM_OFFSET_MAX_ARINC_PBIT (1U)

#define CORE_NVSRAM_OFFSET_MAX_DIN_PBIT   (2U)

#define CORE_NVSRAM_OFFSET_MAX_DOUT_PBIT  (1U)

#define CORE_NVSRAM_OFFSET_MAX_PWM_PBIT   (1U)

#define CORE_NVSRAM_OFFSET_MAX_RVDT_PBIT  (1U)


// Maximum number of offset CBITs

#define CORE_NVSRAM_OFFSET_MAX_PSU_CBIT   (2U)

#define CORE_NVSRAM_OFFSET_MAX_AIN_CBIT   (2U)

#define CORE_NVSRAM_OFFSET_MAX_ARINC_CBIT (2U)

#define CORE_NVSRAM_OFFSET_MAX_DIN_CBIT   (3U)

#define CORE_NVSRAM_OFFSET_MAX_DOUT_CBIT  (7U)

#define CORE_NVSRAM_OFFSET_MAX_PWM_CBIT   (2U)

#define CORE_NVSRAM_OFFSET_MAX_RVDT_CBIT  (3U)


// NVSRAM offset BITs

#define CORE_NVSRAM_OFFSET_PSU_CBIT             (0x00000000U)

#define CORE_NVSRAM_OFFSET_PSU_CBIT_TIMESTAMP   (0x00000008U)

#define CORE_NVSRAM_OFFSET_PWR_FAIL             (0x00000010U)

#define CORE_NVSRAM_OFFSET_PWR_FAIL_TIMESTAMP   (0x00000014U)

#define CORE_NVSRAM_OFFSET_AIN_PBIT             (0x00000080U)

#define CORE_NVSRAM_OFFSET_AIN_PBIT_TIMESTAMP   (0x00000088U)

#define CORE_NVSRAM_OFFSET_AIN_CBIT             (0x00000090U)

#define CORE_NVSRAM_OFFSET_AIN_CBIT_TIMESTAMP   (0x00000098U)

#define CORE_NVSRAM_OFFSET_ARINC_PBIT           (0x00000100U)

#define CORE_NVSRAM_OFFSET_ARINC_PBIT_TIMESTAMP (0x00000104U)

#define CORE_NVSRAM_OFFSET_ARINC_CBIT           (0x0000010CU)

#define CORE_NVSRAM_OFFSET_ARINC_CBIT_TIMESTAMP (0x00000114U)

#define CORE_NVSRAM_OFFSET_DOUT_PBIT            (0x00000180U)

#define CORE_NVSRAM_OFFSET_DOUT_PBIT_TIMESTAMP  (0x00000184U)

#define CORE_NVSRAM_OFFSET_DOUT_CBIT            (0x0000018CU)

#define CORE_NVSRAM_OFFSET_DOUT_CBIT_TIMESTAMP  (0x000001A8U)

#define CORE_NVSRAM_OFFSET_DIN_PBIT             (0x00000200U)

#define CORE_NVSRAM_OFFSET_DIN_PBIT_TIMESTAMP   (0x00000208U)

#define CORE_NVSRAM_OFFSET_DIN_CBIT             (0x00000210U)

#define CORE_NVSRAM_OFFSET_DIN_CBIT_TIMESTAMP   (0x0000021CU)

#define CORE_NVSRAM_OFFSET_PWM_PBIT             (0x00000280U)

#define CORE_NVSRAM_OFFSET_PWM_PBIT_TIMESTAMP   (0x00000284U)

#define CORE_NVSRAM_OFFSET_PWM_CBIT             (0x0000028CU)

#define CORE_NVSRAM_OFFSET_PWM_CBIT_TIMESTAMP   (0x00000294U)

#define CORE_NVSRAM_OFFSET_RVDT_PBIT            (0x00000300U)

#define CORE_NVSRAM_OFFSET_RVDT_PBIT_TIMESTAMP  (0x00000304U)

#define CORE_NVSRAM_OFFSET_RVDT_CBIT            (0x0000030CU)

#define CORE_NVSRAM_OFFSET_RVDT_CBIT_TIMESTAMP  (0x00000318U)


#endif // INCLUDED_CORE_NVSRAM_MAP_H