HFCC-01 Low-Level Software (LLSW) Rel_6802_HFCC-01-RP-CSAR-CB
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inter.h
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1/*
2 * Copyright (c) 2025, TUSAS Malaysia
3 * All rights reserved.
4 * This file contains proprietary information. This
5 * file shall not be duplicated, used, modified,
6 * or disclosed in whole or in part without
7 * the express written consent of TUSAS.
8 */
9
16
17#ifndef INCLUDED_INTER_H
18#define INCLUDED_INTER_H
19
20#include "fswCommonTypes.h"
21
25typedef struct
26{
27 UInt32 deviceNum;
28 UInt32 mfb1Status;
29 UInt32 mfb2Status;
30 UInt32 cfgReady1;
31 UInt32 cfgReady2;
32 UInt32 vendorId1;
33 UInt32 vendorId2;
34} StatusInfo;
35
61void pci_init_hook(StatusInfo *mrStatus);
62
63#endif // INCLUDED_INTER_H
pci_init_hook
void pci_init_hook(StatusInfo *mrStatus)
pci_init_hook.
Definition inter.c:30
StatusInfo
PCI Bus Status and MFB Hardware Readiness Telemetry Structure.
Definition inter.h:26
StatusInfo::vendorId1
UInt32 vendorId1
MFB1 PCI subsystem vendor identifier register value.
Definition inter.h:32
StatusInfo::deviceNum
UInt32 deviceNum
Target PCI device numerical index within MFB chassis.
Definition inter.h:27
StatusInfo::mfb1Status
UInt32 mfb1Status
MFB1 processor and FPGA hardware status register bitmask.
Definition inter.h:28
StatusInfo::cfgReady2
UInt32 cfgReady2
MFB2 hardware configuration and PCIe enumeration readiness flag.
Definition inter.h:31
StatusInfo::mfb2Status
UInt32 mfb2Status
MFB2 processor and FPGA hardware status register bitmask.
Definition inter.h:29
StatusInfo::cfgReady1
UInt32 cfgReady1
MFB1 hardware configuration and PCIe enumeration readiness flag.
Definition inter.h:30
StatusInfo::vendorId2
UInt32 vendorId2
MFB2 PCI subsystem vendor identifier register value.
Definition inter.h:33