modConfig.h

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/*
 * Copyright (c) 2025, TUSAS Malaysia
 * All rights reserved.
 * This file contains proprietary information. This
 * file shall not be duplicated, used, modified,
 * or disclosed in whole or in part without
 * the express written consent of TUSAS.
 */

 
#ifndef INCLUDED_MOD_CONFIG_H
#define INCLUDED_MOD_CONFIG_H
 
#include <INTEGRITY.h>
 
#include "modStatus.h"
#include "modInfo.h"
 
#define MOD_CONFIG_CH_NUM_MASK   (0x000FU)
#define MOD_CONFIG_BNK_NUM_MASK  (0x00F0U)
#define MOD_CONFIG_DEV_NUM_MASK  (0x0F00U)
#define MOD_CONFIG_CARD_NUM_MASK (0xF000U)
#define MOD_CONFIG_BNK_TYPE_MASK (0x00C0U)
 
#define MOD_CONFIG_BNK_NUM_MASK_BIT_SHIFT  (4U)
#define MOD_CONFIG_DEV_NUM_MASK_BIT_SHIFT  (8U)
#define MOD_CONFIG_CARD_NUM_MASK_BIT_SHIFT (12U)
 
#define MOD_CONFIG_GET_CH_NUM(x) (((x) & MOD_CONFIG_CH_NUM_MASK))
#define MOD_CONFIG_GET_BNK_NUM(x)                                                                 \
   ((((x) & MOD_CONFIG_BNK_NUM_MASK) >> MOD_CONFIG_BNK_NUM_MASK_BIT_SHIFT))
#define MOD_CONFIG_GET_BNK_TYPE(x) (((x) & MOD_CONFIG_BNK_TYPE_MASK))
#define MOD_CONFIG_GET_DEV_NUM(x)                                                                 \
   ((((x) & MOD_CONFIG_DEV_NUM_MASK) >> MOD_CONFIG_DEV_NUM_MASK_BIT_SHIFT))
#define MOD_CONFIG_GET_CARD_NUM(x)                                                                \
   ((((x) & MOD_CONFIG_CARD_NUM_MASK) >> MOD_CONFIG_CARD_NUM_MASK_BIT_SHIFT))
 
// =========================================================================
 
// ARINC429 Module
#define MOD_CONFIG_MAX_A429_TX_CH   (4U)
#define MOD_CONFIG_MAX_A429_RX_CH   (7U)
#define MOD_CONFIG_A429_MAX_TX_FIFO (32U)
 
// Analog Input Module
#define MOD_CONFIG_AIN_TOTAL_DEV        (8U)
#define MOD_CONFIG_AIN_MAX_DEV_PER_CARD (8U) // per cards
#define MOD_CONFIG_AIN_MAX_BANK         (2U)
#define MOD_CONFIG_AIN_ADC_FACTOR       (5.0F)
#define MOD_CONFIG_AIN_5V_BANK          (0x00U)
#define MOD_CONFIG_AIN_10V_BANK         (0x01U)
#define MOD_CONFIG_AIN_0V_RANGE         (0U)
#define MOD_CONFIG_AIN_5V_RANGE         (5U)
#define MOD_CONFIG_AIN_10V_RANGE        (10U)
 
// Discrete Input Module
#define MOD_CONFIG_DIN_MAX_CARD         (2U)
#define MOD_CONFIG_DIN_MAX_DEV_PER_CARD (2U) // per cards
#define MOD_CONFIG_DIN_MFB1_DEV         (1U)
#define MOD_CONFIG_DIN_MFB2_DEV         (2U)
#define MOD_CONFIG_DIN_TOTAL_DEV        (MOD_CONFIG_DIN_MFB1_DEV + MOD_CONFIG_DIN_MFB2_DEV)
#define MOD_CONFIG_DIN_MAX_BANK_PER_DEV (4U)
#define MOD_CONFIG_DIN_MAX_CH_PER_BANK  (8U)
#define MOD_CONFIG_DIN_MAX_CH           (38)
#define MOD_CONFIG_DIN_TYPE_OG          (0x40U)
#define MOD_CONFIG_DIN_TYPE_SO          (0x80U)
#define MOD_CONFIG_DIN_TYPE_SG          (0xC0U)
 
// Discrete Out Module
#define MOD_CONFIG_DOUT_MAX_CARD         (2U)
#define MOD_CONFIG_DOUT_MAX_DEV_PER_CARD (8U) // per cards
#define MOD_CONFIG_DOUT_MFB1_DEV         (8U)
#define MOD_CONFIG_DOUT_MFB2_DEV         (3U)
#define MOD_CONFIG_DOUT_TOTAL_DEV        (MOD_CONFIG_DOUT_MFB1_DEV + MOD_CONFIG_DOUT_MFB2_DEV)
#define MOD_CONFIG_DOUT_MAX_CH_PER_DEV   (6U)
#define MOD_CONFIG_DOUT_TYPE_OG          (0x40U)
#define MOD_CONFIG_DOUT_TYPE_SO          (0x80U)
#define MOD_CONFIG_DOUT_TYPE_SG          (0xC0U)
#define MOD_CONFIG_DOUT_TOTAL_CH         (50U)
 
// RVDT Module
#define MOD_CONFIG_RVDT_MAX_DEV_PER_CARD (4U) // per cards
 
// PWM Module
#define MOD_CONFIG_PWM_MAX_DEV_PER_CARD (4U) // per cards
#define MOD_CONFIG_PWM_MAX_CH_PER_DEV   (6U)

typedef enum
{
   A429_TX_CH1 = 0x1000, 
   A429_TX_CH2 = 0x1001, 
   A429_TX_CH3 = 0x1002, 
   A429_TX_CH4 = 0x1003, 
   A429_RX_CH1 = 0x1010, 
   A429_RX_CH2 = 0x1011, 
   A429_RX_CH3 = 0x1012, 
   A429_RX_CH4 = 0x1013, 
   A429_RX_CH5 = 0x1014, 
   A429_RX_CH6 = 0x1015, 
   A429_RX_CH7 = 0x1016 
} A429ChannelNum;

typedef enum
{
   AIN_5V_CH1 = 0x0000, 
   AIN_5V_CH2 = 0x0100, 
   AIN_5V_CH3 = 0x0200, 
   AIN_5V_CH4 = 0x0300, 
   AIN_10V_CH1 = 0x0410, 
   AIN_10V_CH2 = 0x0510, 
   AIN_10V_CH3 = 0x0610, 
   AIN_10V_CH4 = 0x0710 
} AInChannelNum;

typedef enum
{
   DIN_DEV1_BANK = 0x0000, 
   DIN_DEV2_BANK = 0x1000, 
   DIN_DEV3_BANK = 0x1100, 
} DInChannelBank;
 
// DIN Channel Number  //card-device-bank-channel

typedef enum
{
   DIN_SO_CH1 = 0x0000 | MOD_CONFIG_DIN_TYPE_SO, 
   DIN_SO_CH2 = 0x0001 | MOD_CONFIG_DIN_TYPE_SO, 
   DIN_SO_CH3 = 0x0002 | MOD_CONFIG_DIN_TYPE_SO, 
   DIN_SO_CH4 = 0x0003 | MOD_CONFIG_DIN_TYPE_SO, 
   DIN_SO_CH5 = 0x0004 | MOD_CONFIG_DIN_TYPE_SO, 
   DIN_SO_CH6 = 0x0005 | MOD_CONFIG_DIN_TYPE_SO, 
 
   DIN_SO_CH7 = 0x1000 | MOD_CONFIG_DIN_TYPE_SO, 
   DIN_SO_CH8 = 0x1001 | MOD_CONFIG_DIN_TYPE_SO, 
   DIN_SO_CH9 = 0x1002 | MOD_CONFIG_DIN_TYPE_SO, 
   DIN_SO_CH10 = 0x1003 | MOD_CONFIG_DIN_TYPE_SO, 
   DIN_SO_CH11 = 0x1004 | MOD_CONFIG_DIN_TYPE_SO, 
   DIN_SO_CH12 = 0x1005 | MOD_CONFIG_DIN_TYPE_SO, 
   DIN_SO_CH13 = 0x1006 | MOD_CONFIG_DIN_TYPE_SO, 
   DIN_SO_CH14 = 0x1007 | MOD_CONFIG_DIN_TYPE_SO, 
   DIN_SO_CH15 = 0x1020 | MOD_CONFIG_DIN_TYPE_SO, 
   DIN_SO_CH16 = 0x1021 | MOD_CONFIG_DIN_TYPE_SO, 
 
   DIN_OG_CH17 = 0x1110 | MOD_CONFIG_DIN_TYPE_OG, 
   DIN_OG_CH18 = 0x1111 | MOD_CONFIG_DIN_TYPE_OG, 
   DIN_OG_CH19 = 0x1112 | MOD_CONFIG_DIN_TYPE_OG, 
   DIN_OG_CH20 = 0x1113 | MOD_CONFIG_DIN_TYPE_OG, 
   DIN_OG_CH21 = 0x1114 | MOD_CONFIG_DIN_TYPE_OG, 
   DIN_OG_CH22 = 0x1115 | MOD_CONFIG_DIN_TYPE_OG, 
   DIN_OG_CH23 = 0x1116 | MOD_CONFIG_DIN_TYPE_OG, 
   DIN_OG_CH24 = 0x1117 | MOD_CONFIG_DIN_TYPE_OG, 
 
   DIN_OG_CH25 = 0x1130 | MOD_CONFIG_DIN_TYPE_OG, 
   DIN_OG_CH26 = 0x1131 | MOD_CONFIG_DIN_TYPE_OG, 
   DIN_OG_CH27 = 0x1132 | MOD_CONFIG_DIN_TYPE_OG, 
   DIN_OG_CH28 = 0x1133 | MOD_CONFIG_DIN_TYPE_OG, 
   DIN_OG_CH29 = 0x1134 | MOD_CONFIG_DIN_TYPE_OG, 
   DIN_OG_CH30 = 0x1135 | MOD_CONFIG_DIN_TYPE_OG, 
   DIN_OG_CH31 = 0x1136 | MOD_CONFIG_DIN_TYPE_OG, 
   DIN_OG_CH32 = 0x1137 | MOD_CONFIG_DIN_TYPE_OG, 
 
   DIN_SG_CH33 = 0x1022 | MOD_CONFIG_DIN_TYPE_SG, 
   DIN_SG_CH34 = 0x1023 | MOD_CONFIG_DIN_TYPE_SG, 
   DIN_SG_CH35 = 0x1024 | MOD_CONFIG_DIN_TYPE_SG, 
   DIN_SG_CH36 = 0x1025 | MOD_CONFIG_DIN_TYPE_SG, 
   DIN_SG_CH37 = 0x1026 | MOD_CONFIG_DIN_TYPE_SG, 
   DIN_SG_CH38 = 0x1027 | MOD_CONFIG_DIN_TYPE_SG 
} DInChannelNum;

typedef enum
{
   DOUT_DEV1_BANK = 0x0000, 
   DOUT_DEV2_BANK = 0x0100, 
   DOUT_DEV3_BANK = 0x0200, 
   DOUT_DEV4_BANK = 0x0300, 
   DOUT_DEV5_BANK = 0x0400, 
   DOUT_DEV6_BANK = 0x0500, 
   DOUT_DEV7_BANK = 0x0600, 
   DOUT_DEV8_BANK = 0x0700, 
   DOUT_DEV9_BANK = 0x1000, 
   DOUT_DEV10_BANK = 0x1100, 
   DOUT_DEV11_BANK = 0x1200, 
} DOutChannelBank;

typedef enum
{
   DOUT_SO_CW1 = 0x0000 | MOD_CONFIG_DOUT_TYPE_SO, 
   DOUT_SO_CW2 = 0x0100 | MOD_CONFIG_DOUT_TYPE_SO, 
   DOUT_SO_CW3 = 0x0200 | MOD_CONFIG_DOUT_TYPE_SO, 
   DOUT_SO_CW4 = 0x0300 | MOD_CONFIG_DOUT_TYPE_SO, 
 
   DOUT_SO_CCW1 =
      0x0004 | MOD_CONFIG_DOUT_TYPE_SO, 
   DOUT_SO_CCW2 =
      0x0104 | MOD_CONFIG_DOUT_TYPE_SO, 
   DOUT_SO_CCW3 =
      0x0204 | MOD_CONFIG_DOUT_TYPE_SO, 
   DOUT_SO_CCW4 =
      0x0304 | MOD_CONFIG_DOUT_TYPE_SO, 
 
   DOUT_SO_EN1 = 0x0003 | MOD_CONFIG_DOUT_TYPE_SO, 
   DOUT_SO_EN2 = 0x0103 | MOD_CONFIG_DOUT_TYPE_SO, 
   DOUT_SO_EN3 = 0x0203 | MOD_CONFIG_DOUT_TYPE_SO, 
   DOUT_SO_EN4 = 0x0303 | MOD_CONFIG_DOUT_TYPE_SO, 
 
   DOUT_SG_CLCH1 = 0x0005 | MOD_CONFIG_DOUT_TYPE_SG, 
   DOUT_SG_CLCH2 = 0x0105 | MOD_CONFIG_DOUT_TYPE_SG, 
   DOUT_SG_CLCH3 = 0x0205 | MOD_CONFIG_DOUT_TYPE_SG, 
   DOUT_SG_CLCH4 = 0x0305 | MOD_CONFIG_DOUT_TYPE_SG, 
 
   DOUT_SO_EXC1 = 0x0400 | MOD_CONFIG_DOUT_TYPE_SO, 
   DOUT_SO_EXC2 = 0x0404 | MOD_CONFIG_DOUT_TYPE_SO, 
   DOUT_SO_EXC3 = 0x0405 | MOD_CONFIG_DOUT_TYPE_SO, 
   DOUT_SO_EXC4 = 0x0403 | MOD_CONFIG_DOUT_TYPE_SO, 
 
   DOUT_SG_EXT1 = 0x1000 | MOD_CONFIG_DOUT_TYPE_SG, 
   DOUT_SG_EXT2 = 0x1100 | MOD_CONFIG_DOUT_TYPE_SG, 
   DOUT_SG_EXT3 = 0x1003 | MOD_CONFIG_DOUT_TYPE_SG, 
   DOUT_SG_EXT4 = 0x1103 | MOD_CONFIG_DOUT_TYPE_SG, 
 
   DOUT_SG_RET1 = 0x1001 | MOD_CONFIG_DOUT_TYPE_SG, 
   DOUT_SG_RET2 = 0x1101 | MOD_CONFIG_DOUT_TYPE_SG, 
   DOUT_SG_RET3 = 0x1002 | MOD_CONFIG_DOUT_TYPE_SG, 
   DOUT_SG_RET4 = 0x1102 | MOD_CONFIG_DOUT_TYPE_SG, 
 
   DOUT_OG_CH1 = 0x0500 | MOD_CONFIG_DOUT_TYPE_OG, 
   DOUT_OG_CH2 = 0x0504 | MOD_CONFIG_DOUT_TYPE_OG, 
   DOUT_OG_CH3 = 0x0505 | MOD_CONFIG_DOUT_TYPE_OG, 
   DOUT_OG_CH4 = 0x0503 | MOD_CONFIG_DOUT_TYPE_OG, 
   DOUT_OG_CH5 = 0x0501 | MOD_CONFIG_DOUT_TYPE_OG, 
   DOUT_OG_CH6 = 0x0502 | MOD_CONFIG_DOUT_TYPE_OG, 
   DOUT_OG_CH7 = 0x0600 | MOD_CONFIG_DOUT_TYPE_OG, 
   DOUT_OG_CH8 = 0x0604 | MOD_CONFIG_DOUT_TYPE_OG, 
   DOUT_OG_CH9 = 0x0605 | MOD_CONFIG_DOUT_TYPE_OG, 
   DOUT_OG_CH10 = 0x0603 | MOD_CONFIG_DOUT_TYPE_OG, 
   DOUT_OG_CH11 = 0x0601 | MOD_CONFIG_DOUT_TYPE_OG, 
   DOUT_OG_CH12 = 0x0602 | MOD_CONFIG_DOUT_TYPE_OG, 
   DOUT_OG_CH13 = 0x0700 | MOD_CONFIG_DOUT_TYPE_OG, 
   DOUT_OG_CH14 = 0x0704 | MOD_CONFIG_DOUT_TYPE_OG, 
   DOUT_OG_CH15 = 0x0705 | MOD_CONFIG_DOUT_TYPE_OG, 
   DOUT_OG_CH16 = 0x0703 | MOD_CONFIG_DOUT_TYPE_OG, 
 
   DOUT_SO_CH17 = 0x1200 | MOD_CONFIG_DOUT_TYPE_SO, 
   DOUT_SO_CH18 = 0x1204 | MOD_CONFIG_DOUT_TYPE_SO, 
   DOUT_SO_CH19 = 0x1205 | MOD_CONFIG_DOUT_TYPE_SO, 
   DOUT_SO_CH20 = 0x1203 | MOD_CONFIG_DOUT_TYPE_SO, 
   DOUT_SO_CH21 = 0x1201 | MOD_CONFIG_DOUT_TYPE_SO, 
   DOUT_SO_CH22 = 0x1202 | MOD_CONFIG_DOUT_TYPE_SO 
} DOutChannelNum;

typedef enum
{
   RVDT_CH1 = 0x1000, 
   RVDT_CH2 = 0x1100, 
   RVDT_CH3 = 0x1200, 
   RVDT_CH4 = 0x1300 
} RVDTChannelNum;

typedef enum
{
   PWM_CH1 = 0x0002, 
   PWM_CH2 = 0x0102, 
   PWM_CH3 = 0x0202, 
   PWM_CH4 = 0x0302 
} PWMChannelNum;

typedef enum
{
   LED_RED = 1, 
   LED_GREEN = 2, 
   LED_YELLOW = 3, 
   LED_OFF = 4 
} LEDColor;

ModStatus modConfig_coreRegister(const IODevice ioDev, const MemoryRegion nvsramMRDev);

ModStatus modConfig_coreChasisLEDSet(const LEDColor color);

ModStatus modConfig_open(const MemoryRegion cardMfb1MR, const MemoryRegion cardMfb2MR,
                         const MemoryRegion memStatusMR);

ModStatus modConfig_getCardState(const CardType type, ModeState *state);

ModStatus modConfig_init(const UInt32 module);

ModStatus modConfig_reset(const UInt32 modules);

ModStatus modConfig_close(void);
 
#endif // INCLUDED_MOD_CONFIG_H