modHsbCommon.h

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/*
* Copyright (c) 2025, TUSAS Malaysia
* All rights reserved. 
* This file contains proprietary information. This
* file shall not be duplicated, used, modified,
* or disclosed in whole or in part without
* the express written consent of TUSAS.
*/

 
#ifndef INCLUDED_MOD_HSB_COMMON_H
#define INCLUDED_MOD_HSB_COMMON_H
 
#include "commonDataTypes.h"
 
#define MOD_HSB_COMMON_MFB_PBIT_MAX_FAIL_COUNT (5U) 
#define MOD_HSB_COMMON_MFB_CBIT_MAX_FAIL_COUNT (7U) 
 
#define MOD_HSB_COMMON_AIN_PBIT_MAX_FAIL_COUNT (37U) 
#define MOD_HSB_COMMON_AIN_CBIT_MAX_FAIL_COUNT (37U) 
 
#define MOD_HSB_COMMON_A429_PBIT_MAX_FAIL_COUNT (23U) 
#define MOD_HSB_COMMON_A429_CBIT_MAX_FAIL_COUNT (38U) 
 
#define MOD_HSB_COMMON_DIN_PBIT_MAX_FAIL_COUNT (56U) 
#define MOD_HSB_COMMON_DIN_CBIT_MAX_FAIL_COUNT (68U) 
 
#define MOD_HSB_COMMON_DOUT_PBIT_MAX_FAIL_COUNT (20U) 
#define MOD_HSB_COMMON_DOUT_CBIT_MAX_FAIL_COUNT (224U) 
 
#define MOD_HSB_COMMON_PSU_CBIT_MAX_FAIL_COUNT (34U) 
 
#define MOD_HSB_COMMON_PWM_PBIT_MAX_FAIL_COUNT (9U) 
#define MOD_HSB_COMMON_PWM_CBIT_MAX_FAIL_COUNT (41U) 
 
#define MOD_HSB_COMMON_RVDT_PBIT_MAX_FAIL_COUNT (22U) 
#define MOD_HSB_COMMON_RVDT_CBIT_MAX_FAIL_COUNT (77U) 

typedef enum
{
   MFB_PBIT_SUCCESS = 0U, 
   MFB_PBIT_MFB1_NOT_READY = 1U, 
   MFB_PBIT_MFB2_NOT_READY = 2U, 
   MFB_PBIT_MFB1_INCOMPLETE = 1U, 
   MFB_PBIT_MFB2_INCOMPLETE = 2U, 
   MFB_PBIT_MFB1_CARD_OPEN_FAIL = 3U, 
   MFB_PBIT_MFB2_CARD_OPEN_FAIL = 4U, 
} MfbPBITFailCode;

typedef enum
{
   MFB_CBIT_SUCCESS = 0U, 
   MFB_CBIT_MFB1_NOT_RUN = 1U, 
   MFB_CBIT_MFB2_NOT_RUN = 2U, 
   MFB_CBIT_MFB1_NOT_READY = 3U, 
   MFB_CBIT_MFB2_NOT_READY = 4U, 
   MFB_CBIT_MFB1_CARD_OPEN_FAIL = 5U, 
   MFB_CBIT_MFB2_CARD_OPEN_FAIL = 6U, 
} MfbCBITFailCode;

typedef enum
{
   A429_PBIT_SUCCESS = 0U, 
   A429_PBIT_PWR_FAULT = 1U, 
   A429_PBIT_IC_NOT_READY = 2U, 
   A429_PBIT_COMM_ERR = 3U, 
   A429_PBIT_BIST_ERR = 4U, 
   A429_PBIT_LOOPBACK_TX_CH1_ERR = 5U, 
   A429_PBIT_LOOPBACK_TX_CH2_ERR = 6U, 
   A429_PBIT_LOOPBACK_TX_CH3_ERR = 7U, 
   A429_PBIT_LOOPBACK_TX_CH4_ERR = 8U, 
   A429_PBIT_LOOPBACK_RX_CH1_ERR = 9U, 
   A429_PBIT_LOOPBACK_RX_CH2_ERR = 10U, 
   A429_PBIT_LOOPBACK_RX_CH3_ERR = 11U, 
   A429_PBIT_LOOPBACK_RX_CH4_ERR = 12U, 
   A429_PBIT_LOOPBACK_RX_CH5_ERR = 13U, 
   A429_PBIT_LOOPBACK_RX_CH6_ERR = 14U, 
   A429_PBIT_LOOPBACK_RX_CH7_ERR = 15U, 
   A429_PBIT_NOT_DONE = 16U, 
   A429_PBIT_RAM_BIST_NOT_DONE = 17U, 
   A429_PBIT_RAM_BIST_FAIL = 18U, 
   A429_PBIT_BIST_UPPERBIT_FAIL = 19U, 
   A429_PBIT_BIST_LOWERBIT_FAIL = 20U, 
   A429_PBIT_CARD_OPEN_FAIL = 21U, 
   A429_PBIT_MOD_INIT_FAIL = 22U 
} A429PBITFailCode;

typedef enum
{
   A429_CBIT_SUCCESS = 0U, 
   A429_CBIT_NOT_DONE = 1U, 
   A429_CBIT_PWR_FAULT_3V3 = 2U, 
   A429_CBIT_PWR_FAULT_BIT = 3U, 
   A429_CBIT_PWR_FAULT_ISO = 4U, 
   A429_CBIT_PWR_FAULT_TX_DRV = 5U, 
   A429_CBIT_UNDER_TEMP = 6U, 
   A429_CBIT_OVER_TEMP = 7U, 
   A429_CBIT_IC_NOT_READY = 8U, 
   A429_CBIT_COMM_ERR = 9U, 
   A429_CBIT_TX_LOOPBACK_NOT_READY = 10U, 
   A429_CBIT_TX_LOOPBACK_COMM_ERR = 11U, 
   A429_CBIT_RX_LOOPBACK_NOT_READY = 12U, 
   A429_CBIT_RX_LOOPBACK_COMM_ERR = 13U, 
   A429_CBIT_MISMATCH_TXCH1 = 14U, 
   A429_CBIT_MISMATCH_TXCH2 = 15U, 
   A429_CBIT_MISMATCH_TXCH3 = 16U, 
   A429_CBIT_MISMATCH_TXCH4 = 17U, 
   A429_CBIT_MISMATCH_RXCH1 = 18U, 
   A429_CBIT_MISMATCH_RXCH2 = 19U, 
   A429_CBIT_MISMATCH_RXCH3 = 20U, 
   A429_CBIT_MISMATCH_RXCH4 = 21U, 
   A429_CBIT_MISMATCH_RXCH5 = 22U, 
   A429_CBIT_MISMATCH_RXCH6 = 23U, 
   A429_CBIT_MISMATCH_RXCH7 = 24U, 
   A429_CBIT_RECEIVE_TXCH1 = 25U, 
   A429_CBIT_RECEIVE_TXCH2 = 26U, 
   A429_CBIT_RECEIVE_TXCH3 = 27U, 
   A429_CBIT_RECEIVE_TXCH4 = 28U, 
   A429_CBIT_RECEIVE_RXCH1 = 29U, 
   A429_CBIT_RECEIVE_RXCH2 = 30U, 
   A429_CBIT_RECEIVE_RXCH3 = 31U, 
   A429_CBIT_RECEIVE_RXCH4 = 32U, 
   A429_CBIT_RECEIVE_RXCH5 = 33U, 
   A429_CBIT_RECEIVE_RXCH6 = 34U, 
   A429_CBIT_RECEIVE_RXCH7 = 35U, 
   A429_CBIT_CARD_OPEN_FAIL = 36U, 
   A429_CBIT_MOD_INIT_FAIL = 37U 
} A429CBITFailCode;

typedef enum
{
   AIN_PBIT_SUCCESS = 0U, 
   AIN_PBIT_INCOMPLETED = 1U, 
   AIN_PBIT_3V3_FAULT = 2U, 
   AIN_PBIT_5V_FAULT = 3U, 
   AIN_PBIT_15V_FAULT = 4U, 
   AIN_PBIT_UT_BANK0_FAULT = 5U, 
   AIN_PBIT_OT_BANK0_FAULT = 6U, 
   AIN_PBIT_UT_BANK1_FAULT = 7U, 
   AIN_PBIT_OT_BANK1_FAULT = 8U, 
   AIN_PBIT_IC_COMM_ERR_CH1_FAULT = 9U, 
   AIN_PBIT_IC_COMM_ERR_CH2_FAULT = 10U, 
   AIN_PBIT_IC_COMM_ERR_CH3_FAULT = 11U, 
   AIN_PBIT_IC_COMM_ERR_CH4_FAULT = 12U, 
   AIN_PBIT_IC_COMM_ERR_CH5_FAULT = 13U, 
   AIN_PBIT_IC_COMM_ERR_CH6_FAULT = 14U, 
   AIN_PBIT_IC_COMM_ERR_CH7_FAULT = 15U, 
   AIN_PBIT_IC_COMM_ERR_CH8_FAULT = 16U, 
   AIN_PBIT_IC_COMM_ERR_LB_BANK0_FAULT = 17U, 
   AIN_PBIT_IC_COMM_ERR_LB_BANK1_FAULT = 18U, 
   AIN_PBIT_OVP_CH1_FAULT = 19U,  
   AIN_PBIT_OVP_CH2_FAULT = 20U,  
   AIN_PBIT_OVP_CH3_FAULT = 21U,  
   AIN_PBIT_OVP_CH4_FAULT = 22U,  
   AIN_PBIT_OVP_CH5_FAULT = 23U,  
   AIN_PBIT_OVP_CH6_FAULT = 24U,  
   AIN_PBIT_OVP_CH7_FAULT = 25U,  
   AIN_PBIT_OVP_CH8_FAULT = 26U,  
   AIN_PBIT_IVR_ERR_CH1_FAULT = 27U, 
   AIN_PBIT_IVR_ERR_CH2_FAULT = 28U, 
   AIN_PBIT_IVR_ERR_CH3_FAULT = 29U, 
   AIN_PBIT_IVR_ERR_CH4_FAULT = 30U, 
   AIN_PBIT_IVR_ERR_CH5_FAULT = 31U, 
   AIN_PBIT_IVR_ERR_CH6_FAULT = 32U, 
   AIN_PBIT_IVR_ERR_CH7_FAULT = 33U, 
   AIN_PBIT_IVR_ERR_CH8_FAULT = 34U, 
   AIN_PBIT_CARD_OPEN_FAIL = 35U, 
   AIN_PBIT_MOD_INIT_FAIL = 36U 
} AInPBITFailCode;

typedef enum
{
   AIN_CBIT_SUCCESS = 0U, 
   AIN_CBIT_NOT_RUN_FAULT = 1U, 
   AIN_CBIT_3V3_FAULT = 2U, 
   AIN_CBIT_5V_FAULT = 3U, 
   AIN_CBIT_15V_FAULT = 4U, 
   AIN_CBIT_UT_BANK0_FAULT = 5U, 
   AIN_CBIT_OT_BANK0_FAULT = 6U, 
   AIN_CBIT_UT_BANK1_FAULT = 7U, 
   AIN_CBIT_OT_BANK1_FAULT = 8U, 
   AIN_CBIT_IC_COMM_ERR_CH1_FAULT = 9U, 
   AIN_CBIT_IC_COMM_ERR_CH2_FAULT = 10U, 
   AIN_CBIT_IC_COMM_ERR_CH3_FAULT = 11U, 
   AIN_CBIT_IC_COMM_ERR_CH4_FAULT = 12U, 
   AIN_CBIT_IC_COMM_ERR_CH5_FAULT = 13U, 
   AIN_CBIT_IC_COMM_ERR_CH6_FAULT = 14U, 
   AIN_CBIT_IC_COMM_ERR_CH7_FAULT = 15U, 
   AIN_CBIT_IC_COMM_ERR_CH8_FAULT = 16U, 
   AIN_CBIT_IC_COMM_ERR_LB_BANK0_FAULT = 17U, 
   AIN_CBIT_IC_COMM_ERR_LB_BANK1_FAULT = 18U, 
   AIN_CBIT_OVP_CH1_FAULT = 19U, 
   AIN_CBIT_OVP_CH2_FAULT = 20U, 
   AIN_CBIT_OVP_CH3_FAULT = 21U, 
   AIN_CBIT_OVP_CH4_FAULT = 22U, 
   AIN_CBIT_OVP_CH5_FAULT = 23U, 
   AIN_CBIT_OVP_CH6_FAULT = 24U, 
   AIN_CBIT_OVP_CH7_FAULT = 25U, 
   AIN_CBIT_OVP_CH8_FAULT = 26U, 
   AIN_CBIT_IVR_ERR_CH1_FAULT = 27U, 
   AIN_CBIT_IVR_ERR_CH2_FAULT = 28U, 
   AIN_CBIT_IVR_ERR_CH3_FAULT = 29U, 
   AIN_CBIT_IVR_ERR_CH4_FAULT = 30U, 
   AIN_CBIT_IVR_ERR_CH5_FAULT = 31U, 
   AIN_CBIT_IVR_ERR_CH6_FAULT = 32U, 
   AIN_CBIT_IVR_ERR_CH7_FAULT = 33U, 
   AIN_CBIT_IVR_ERR_CH8_FAULT = 34U, 
   AIN_CBIT_CARD_OPEN_FAIL = 35U, 
   AIN_CBIT_MOD_INIT_FAIL = 36U 
} AInCBITFailCode;

typedef enum
{
   DIN_PBIT_SUCCESS = 0U, 
   DIN_PBIT_NOT_DONE_1 = 1U, 
   DIN_PBIT_NOT_DONE_2 = 2U, 
   DIN_PBIT_PWR_3V3_FAULT_1 = 3U, 
   DIN_PBIT_PWR_3V3_FAULT_2 = 4U, 
   DIN_PBIT_DEV1_COMM_ERR = 5U, 
   DIN_PBIT_DEV2_COMM_ERR = 6U, 
   DIN_PBIT_DEV3_COMM_ERR = 7U, 
   DIN_PBIT_SO_CH1_FAULT = 8U, 
   DIN_PBIT_SO_CH2_FAULT = 9U, 
   DIN_PBIT_SO_CH3_FAULT = 10U, 
   DIN_PBIT_SO_CH4_FAULT = 11U, 
   DIN_PBIT_SO_CH5_FAULT = 12U, 
   DIN_PBIT_SO_CH6_FAULT = 13U, 
   DIN_PBIT_SO_CH7_FAULT = 14U, 
   DIN_PBIT_SO_CH8_FAULT = 15U, 
   DIN_PBIT_SO_CH9_FAULT = 16U, 
   DIN_PBIT_SO_CH10_FAULT = 17U, 
   DIN_PBIT_SO_CH11_FAULT = 18U, 
   DIN_PBIT_SO_CH12_FAULT = 19U, 
   DIN_PBIT_SO_CH13_FAULT = 20U, 
   DIN_PBIT_SO_CH14_FAULT = 21U, 
   DIN_PBIT_SO_CH15_FAULT = 22U, 
   DIN_PBIT_SO_CH16_FAULT = 23U, 
   DIN_PBIT_SG_CH33_1_FAULT = 24U, 
   DIN_PBIT_SG_CH34_1_FAULT = 25U, 
   DIN_PBIT_SG_CH35_1_FAULT = 26U, 
   DIN_PBIT_SG_CH36_1_FAULT = 27U, 
   DIN_PBIT_SG_CH37_1_FAULT = 28U, 
   DIN_PBIT_SG_CH38_1_FAULT = 29U, 
   DIN_PBIT_GO_CH38_2_FAULT = 30U, 
   DIN_PBIT_GO_CH37_2_FAULT = 31U, 
   DIN_PBIT_GO_CH36_2_FAULT = 32U, 
   DIN_PBIT_GO_CH35_2_FAULT = 33U, 
   DIN_PBIT_GO_CH34_2_FAULT = 34U, 
   DIN_PBIT_GO_CH33_2_FAULT = 35U, 
   DIN_PBIT_GO_CH17_FAULT = 36U, 
   DIN_PBIT_GO_CH18_FAULT = 37U, 
   DIN_PBIT_GO_CH19_FAULT = 38U, 
   DIN_PBIT_GO_CH20_FAULT = 39U, 
   DIN_PBIT_GO_CH21_FAULT = 40U, 
   DIN_PBIT_GO_CH22_FAULT = 41U, 
   DIN_PBIT_GO_CH23_FAULT = 42U, 
   DIN_PBIT_GO_CH24_FAULT = 43U, 
   DIN_PBIT_GO_CH25_FAULT = 44U, 
   DIN_PBIT_GO_CH26_FAULT = 45U, 
   DIN_PBIT_GO_CH27_FAULT = 46U, 
   DIN_PBIT_GO_CH28_FAULT = 47U, 
   DIN_PBIT_GO_CH29_FAULT = 48U, 
   DIN_PBIT_GO_CH30_FAULT = 49U, 
   DIN_PBIT_GO_CH31_FAULT = 50U, 
   DIN_PBIT_GO_CH32_FAULT = 51U, 
   DIN_PBIT_CARD_1_OPEN_FAIL = 52U, 
   DIN_PBIT_CARD_2_OPEN_FAIL = 53U, 
   DIN_PBIT_MOD_1_INIT_FAIL = 54U, 
   DIN_PBIT_MOD_2_INIT_FAIL = 55U 
} DInPBITFailCode;

typedef enum
{
   DIN_CBIT_SUCCESS = 0U, 
   DIN_CBIT_NOT_DONE_1 = 1U, 
   DIN_CBIT_NOT_DONE_2 = 2U, 
   DIN_CBIT_PWR_3V3_FAULT_1 = 3U, 
   DIN_CBIT_PWR_3V3_FAULT_2 = 4U, 
   DIN_CBIT_DEV1_COMM_ERR = 5U, 
   DIN_CBIT_DEV2_COMM_ERR = 6U, 
   DIN_CBIT_DEV3_COMM_ERR = 7U, 
   DIN_CBIT_UNDER_TEMP_1 = 8U, 
   DIN_CBIT_UNDER_TEMP_2 = 9U, 
   DIN_CBIT_OVER_TEMP_1 = 10U, 
   DIN_CBIT_OVER_TEMP_2 = 11U, 
   DIN_CBIT_F_3V3_FAULT_1 = 12U, 
   DIN_CBIT_F_3V3_FAULT_2 = 13U, 
   DIN_CBIT_F_VWET_FAULT_1 = 14U, 
   DIN_CBIT_F_VWET_FAULT_2 = 15U, 
   DIN_CBIT_F_3V3_BIT_FAULT_1 = 16U, 
   DIN_CBIT_F_3V3_BIT_FAULT_2 = 17U, 
   DIN_CBIT_F_VWET_BIT_FAULT_1 = 18U, 
   DIN_CBIT_F_VWET_BIT_FAULT_2 = 19U, 
   DIN_CBIT_SO_CH1_FAULT = 20U, 
   DIN_CBIT_SO_CH2_FAULT = 21U, 
   DIN_CBIT_SO_CH3_FAULT = 22U, 
   DIN_CBIT_SO_CH4_FAULT = 23U, 
   DIN_CBIT_SO_CH5_FAULT = 24U, 
   DIN_CBIT_SO_CH6_FAULT = 25U, 
   DIN_CBIT_SO_CH7_FAULT = 26U, 
   DIN_CBIT_SO_CH8_FAULT = 27U, 
   DIN_CBIT_SO_CH9_FAULT = 28U, 
   DIN_CBIT_SO_CH10_FAULT = 29U, 
   DIN_CBIT_SO_CH11_FAULT = 30U, 
   DIN_CBIT_SO_CH12_FAULT = 31U, 
   DIN_CBIT_SO_CH13_FAULT = 32U, 
   DIN_CBIT_SO_CH14_FAULT = 33U, 
   DIN_CBIT_SO_CH15_FAULT = 34U, 
   DIN_CBIT_SO_CH16_FAULT = 35U, 
   DIN_CBIT_SG_CH33_1_FAULT = 36U, 
   DIN_CBIT_SG_CH34_1_FAULT = 37U, 
   DIN_CBIT_SG_CH35_1_FAULT = 38U, 
   DIN_CBIT_SG_CH36_1_FAULT = 39U, 
   DIN_CBIT_SG_CH37_1_FAULT = 40U, 
   DIN_CBIT_SG_CH38_1_FAULT = 41U, 
   DIN_CBIT_GO_CH38_2_FAULT = 42U, 
   DIN_CBIT_GO_CH37_2_FAULT = 43U, 
   DIN_CBIT_GO_CH36_2_FAULT = 44U, 
   DIN_CBIT_GO_CH35_2_FAULT = 45U, 
   DIN_CBIT_GO_CH34_2_FAULT = 46U, 
   DIN_CBIT_GO_CH33_2_FAULT = 47U, 
   DIN_CBIT_GO_CH17_FAULT = 48U, 
   DIN_CBIT_GO_CH18_FAULT = 49U, 
   DIN_CBIT_GO_CH19_FAULT = 50U, 
   DIN_CBIT_GO_CH20_FAULT = 51U, 
   DIN_CBIT_GO_CH21_FAULT = 52U, 
   DIN_CBIT_GO_CH22_FAULT = 53U, 
   DIN_CBIT_GO_CH23_FAULT = 54U, 
   DIN_CBIT_GO_CH24_FAULT = 55U, 
   DIN_CBIT_GO_CH25_FAULT = 56U, 
   DIN_CBIT_GO_CH26_FAULT = 57U, 
   DIN_CBIT_GO_CH27_FAULT = 58U, 
   DIN_CBIT_GO_CH28_FAULT = 59U, 
   DIN_CBIT_GO_CH29_FAULT = 60U, 
   DIN_CBIT_GO_CH30_FAULT = 61U, 
   DIN_CBIT_GO_CH31_FAULT = 62U, 
   DIN_CBIT_GO_CH32_FAULT = 63U, 
   DIN_CBIT_CARD_1_OPEN_FAIL = 64U, 
   DIN_CBIT_CARD_2_OPEN_FAIL = 65U, 
   DIN_CBIT_MOD_1_INIT_FAIL = 66U, 
   DIN_CBIT_MOD_2_INIT_FAIL = 67U 
} DInCBITFailCode;

typedef enum
{
   DOUT_PBIT_SUCCESS = 0U, 
   DOUT_PBIT_NOT_DONE_1 = 1U, 
   DOUT_PBIT_NOT_DONE_2 = 2U, 
   DOUT_PBIT_CHECK_BANK_1 = 3U, 
   DOUT_PBIT_CHECK_BANK_2 = 4U, 
   DOUT_PBIT_DEV1_FAULT = 5U, 
   DOUT_PBIT_DEV2_FAULT = 6U, 
   DOUT_PBIT_DEV3_FAULT = 7U, 
   DOUT_PBIT_DEV4_FAULT = 8U, 
   DOUT_PBIT_DEV5_FAULT = 9U, 
   DOUT_PBIT_DEV6_FAULT = 10U, 
   DOUT_PBIT_DEV7_FAULT = 11U, 
   DOUT_PBIT_DEV8_FAULT = 12U, 
   DOUT_PBIT_DEV9_FAULT = 13U, 
   DOUT_PBIT_DEV10_FAULT = 14U, 
   DOUT_PBIT_DEV11_FAULT = 15U, 
   DOUT_PBIT_CARD_1_OPEN_FAIL = 16U, 
   DOUT_PBIT_CARD_2_OPEN_FAIL = 17U, 
   DOUT_PBIT_MOD_1_INIT_FAIL = 18U, 
   DOUT_PBIT_MOD_2_INIT_FAIL = 19U 
} DOutPBITFailCode;

typedef enum
{
   DOUT_CBIT_SUCCESS = 0U, 
   DOUT_CBIT_NOT_RUN_1 = 1U, 
   DOUT_CBIT_NOT_RUN_2 = 2U, 
   DOUT_CBIT_PG_3V3_1 = 3U, 
   DOUT_CBIT_PG_3V3_2 = 4U, 
   DOUT_CBIT_UT_FAULT_1 = 5U, 
   DOUT_CBIT_UT_FAULT_2 = 6U, 
   DOUT_CBIT_OT_FAULT_1 = 7U, 
   DOUT_CBIT_OT_FAULT_2 = 8U, 
   DOUT_CBIT_UT_BIT_FAULT = 9U, 
   DOUT_CBIT_OT_BIT_FAULT = 10U, 
   DOUT_CBIT_MAIN_COMM_ERR = 11U, 
   DOUT_CBIT_3V3_FAULT = 12U, 
   DOUT_CBIT_28V_FAULT = 13U, 
   DOUT_CBIT_3V3_BIT_FAULT = 14U, 
   DOUT_CBIT_VWET_BIT_FAULT = 15U, 
 
   DOUT_CBIT_LB_NOT_RUN_IC1 = 16U, 
   DOUT_CBIT_LB_NOT_RUN_IC2 = 17U, 
   DOUT_CBIT_LB_PG_3V3_IC1 = 18U, 
   DOUT_CBIT_LB_PG_3V3_IC2 = 19U, 
   DOUT_CBIT_LB_COMM_ERR_IC1 = 20U, 
   DOUT_CBIT_LB_COMM_ERR_IC2 = 21U, 
   DOUT_CBIT_LB_NOT_RUN = 22U, 
   DOUT_CBIT_LB_PG_3V3 = 23U, 
   DOUT_CBIT_LB_COMM_ERR = 24U, 
 
   DOUT_CBIT_TW_DEV1_FAULT = 25U, 
   DOUT_CBIT_TW_DEV2_FAULT = 26U, 
   DOUT_CBIT_TW_DEV3_FAULT = 27U, 
   DOUT_CBIT_TW_DEV4_FAULT = 28U, 
   DOUT_CBIT_TW_DEV5_FAULT = 29U, 
   DOUT_CBIT_TW_DEV6_FAULT = 30U, 
   DOUT_CBIT_TW_DEV7_FAULT = 31U, 
   DOUT_CBIT_TW_DEV8_FAULT = 32U, 
   DOUT_CBIT_TW_DEV9_FAULT = 33U, 
   DOUT_CBIT_TW_DEV10_FAULT = 34U, 
   DOUT_CBIT_TW_DEV11_FAULT = 35U, 
 
   DOUT_CBIT_PSF_DEV1_FAULT = 36U, 
   DOUT_CBIT_PSF_DEV2_FAULT = 37U, 
   DOUT_CBIT_PSF_DEV3_FAULT = 38U, 
   DOUT_CBIT_PSF_DEV4_FAULT = 39U, 
   DOUT_CBIT_PSF_DEV5_FAULT = 40U, 
   DOUT_CBIT_PSF_DEV6_FAULT = 41U, 
   DOUT_CBIT_PSF_DEV7_FAULT = 42U, 
   DOUT_CBIT_PSF_DEV8_FAULT = 43U, 
   DOUT_CBIT_PSF_DEV9_FAULT = 44U, 
   DOUT_CBIT_PSF_DEV10_FAULT = 45U, 
   DOUT_CBIT_PSF_DEV11_FAULT = 46U, 
 
   DOUT_CBIT_TS_DEV1_FAULT = 47U, 
   DOUT_CBIT_TS_DEV2_FAULT = 48U, 
   DOUT_CBIT_TS_DEV3_FAULT = 49U, 
   DOUT_CBIT_TS_DEV4_FAULT = 50U, 
   DOUT_CBIT_TS_DEV5_FAULT = 51U, 
   DOUT_CBIT_TS_DEV6_FAULT = 52U, 
   DOUT_CBIT_TS_DEV7_FAULT = 53U, 
   DOUT_CBIT_TS_DEV8_FAULT = 54U, 
   DOUT_CBIT_TS_DEV9_FAULT = 55U, 
   DOUT_CBIT_TS_DEV10_FAULT = 56U, 
   DOUT_CBIT_TS_DEV11_FAULT = 57U, 
 
   DOUT_CBIT_SO_CW1_OC_FAULT = 58U, 
   DOUT_CBIT_SO_CW2_OC_FAULT = 59U, 
   DOUT_CBIT_SO_CW3_OC_FAULT = 60U, 
   DOUT_CBIT_SO_CW4_OC_FAULT = 61U, 
   DOUT_CBIT_SO_CCW1_OC_FAULT = 62U, 
   DOUT_CBIT_SO_CCW2_OC_FAULT = 63U, 
   DOUT_CBIT_SO_CCW3_OC_FAULT = 64U, 
   DOUT_CBIT_SO_CCW4_OC_FAULT = 65U, 
   DOUT_CBIT_SO_EN1_OC_FAULT = 66U, 
   DOUT_CBIT_SO_EN2_OC_FAULT = 67U, 
   DOUT_CBIT_SO_EN3_OC_FAULT = 68U, 
   DOUT_CBIT_SO_EN4_OC_FAULT = 69U, 
   DOUT_CBIT_SG_CLCH1_OC_FAULT = 70U, 
   DOUT_CBIT_SG_CLCH2_OC_FAULT = 71U, 
   DOUT_CBIT_SG_CLCH3_OC_FAULT = 72U, 
   DOUT_CBIT_SG_CLCH4_OC_FAULT = 73U, 
   DOUT_CBIT_SO_EXC1_OC_FAULT = 74U, 
   DOUT_CBIT_SO_EXC2_OC_FAULT = 75U, 
   DOUT_CBIT_SO_EXC3_OC_FAULT = 76U, 
   DOUT_CBIT_SO_EXC4_OC_FAULT = 77U, 
   DOUT_CBIT_SG_EXT1_OC_FAULT = 78U, 
   DOUT_CBIT_SG_EXT2_OC_FAULT = 79U, 
   DOUT_CBIT_SG_EXT3_OC_FAULT = 80U, 
   DOUT_CBIT_SG_EXT4_OC_FAULT = 81U, 
   DOUT_CBIT_SG_RET1_OC_FAULT = 82U, 
   DOUT_CBIT_SG_RET2_OC_FAULT = 83U, 
   DOUT_CBIT_SG_RET3_OC_FAULT = 84U, 
   DOUT_CBIT_SG_RET4_OC_FAULT = 85U, 
   DOUT_CBIT_OG_CH1_OC_FAULT = 86U, 
   DOUT_CBIT_OG_CH2_OC_FAULT = 87U, 
   DOUT_CBIT_OG_CH3_OC_FAULT = 88U, 
   DOUT_CBIT_OG_CH4_OC_FAULT = 89U, 
   DOUT_CBIT_OG_CH5_OC_FAULT = 90U, 
   DOUT_CBIT_OG_CH6_OC_FAULT = 91U, 
   DOUT_CBIT_OG_CH7_OC_FAULT = 92U, 
   DOUT_CBIT_OG_CH8_OC_FAULT = 93U, 
   DOUT_CBIT_OG_CH9_OC_FAULT = 94U, 
   DOUT_CBIT_OG_CH10_OC_FAULT = 95U, 
   DOUT_CBIT_OG_CH11_OC_FAULT = 96U, 
   DOUT_CBIT_OG_CH12_OC_FAULT = 97U, 
   DOUT_CBIT_OG_CH13_OC_FAULT = 98U, 
   DOUT_CBIT_OG_CH14_OC_FAULT = 99U, 
   DOUT_CBIT_OG_CH15_OC_FAULT = 100U, 
   DOUT_CBIT_OG_CH16_OC_FAULT = 101U, 
   DOUT_CBIT_SO_CH17_OC_FAULT = 102U, 
   DOUT_CBIT_SO_CH18_OC_FAULT = 103U, 
   DOUT_CBIT_SO_CH19_OC_FAULT = 104U, 
   DOUT_CBIT_SO_CH20_OC_FAULT = 105U, 
   DOUT_CBIT_SO_CH21_OC_FAULT = 106U, 
   DOUT_CBIT_SO_CH22_OC_FAULT = 107U, 
 
   DOUT_CBIT_SO_CW1_ULD_FAULT = 108U, 
   DOUT_CBIT_SO_CW2_ULD_FAULT = 109U, 
   DOUT_CBIT_SO_CW3_ULD_FAULT = 110U, 
   DOUT_CBIT_SO_CW4_ULD_FAULT = 111U, 
   DOUT_CBIT_SO_CCW1_ULD_FAULT = 112U, 
   DOUT_CBIT_SO_CCW2_ULD_FAULT = 113U, 
   DOUT_CBIT_SO_CCW3_ULD_FAULT = 114U, 
   DOUT_CBIT_SO_CCW4_ULD_FAULT = 115U, 
   DOUT_CBIT_SO_EN1_ULD_FAULT = 116U, 
   DOUT_CBIT_SO_EN2_ULD_FAULT = 117U, 
   DOUT_CBIT_SO_EN3_ULD_FAULT = 118U, 
   DOUT_CBIT_SO_EN4_ULD_FAULT = 119U, 
   DOUT_CBIT_SG_CLCH1_ULD_FAULT = 120U, 
   DOUT_CBIT_SG_CLCH2_ULD_FAULT = 121U, 
   DOUT_CBIT_SG_CLCH3_ULD_FAULT = 122U, 
   DOUT_CBIT_SG_CLCH4_ULD_FAULT = 123U, 
   DOUT_CBIT_SO_EXC1_ULD_FAULT = 124U, 
   DOUT_CBIT_SO_EXC2_ULD_FAULT = 125U, 
   DOUT_CBIT_SO_EXC3_ULD_FAULT = 126U, 
   DOUT_CBIT_SO_EXC4_ULD_FAULT = 127U, 
   DOUT_CBIT_SG_EXT1_ULD_FAULT = 128U, 
   DOUT_CBIT_SG_EXT2_ULD_FAULT = 129U, 
   DOUT_CBIT_SG_EXT3_ULD_FAULT = 130U, 
   DOUT_CBIT_SG_EXT4_ULD_FAULT = 131U, 
   DOUT_CBIT_SG_RET1_ULD_FAULT = 132U, 
   DOUT_CBIT_SG_RET2_ULD_FAULT = 133U, 
   DOUT_CBIT_SG_RET3_ULD_FAULT = 134U, 
   DOUT_CBIT_SG_RET4_ULD_FAULT = 135U, 
   DOUT_CBIT_OG_CH1_ULD_FAULT = 136U, 
   DOUT_CBIT_OG_CH2_ULD_FAULT = 137U, 
   DOUT_CBIT_OG_CH3_ULD_FAULT = 138U, 
   DOUT_CBIT_OG_CH4_ULD_FAULT = 139U, 
   DOUT_CBIT_OG_CH5_ULD_FAULT = 140U, 
   DOUT_CBIT_OG_CH6_ULD_FAULT = 141U, 
   DOUT_CBIT_OG_CH7_ULD_FAULT = 142U, 
   DOUT_CBIT_OG_CH8_ULD_FAULT = 143U, 
   DOUT_CBIT_OG_CH9_ULD_FAULT = 144U, 
   DOUT_CBIT_OG_CH10_ULD_FAULT = 145U, 
   DOUT_CBIT_OG_CH11_ULD_FAULT = 146U, 
   DOUT_CBIT_OG_CH12_ULD_FAULT = 147U, 
   DOUT_CBIT_OG_CH13_ULD_FAULT = 148U, 
   DOUT_CBIT_OG_CH14_ULD_FAULT = 149U, 
   DOUT_CBIT_OG_CH15_ULD_FAULT = 150U, 
   DOUT_CBIT_OG_CH16_ULD_FAULT = 151U, 
   DOUT_CBIT_SO_CH17_ULD_FAULT = 152U, 
   DOUT_CBIT_SO_CH18_ULD_FAULT = 153U, 
   DOUT_CBIT_SO_CH19_ULD_FAULT = 154U, 
   DOUT_CBIT_SO_CH20_ULD_FAULT = 155U, 
   DOUT_CBIT_SO_CH21_ULD_FAULT = 156U, 
   DOUT_CBIT_SO_CH22_ULD_FAULT = 157U, 
 
   DOUT_CBIT_SO_CW1_FAULT = 158U, 
   DOUT_CBIT_SO_CW2_FAULT = 159U, 
   DOUT_CBIT_SO_CW3_FAULT = 160U, 
   DOUT_CBIT_SO_CW4_FAULT = 161U, 
   DOUT_CBIT_SO_CCW1_FAULT = 162U, 
   DOUT_CBIT_SO_CCW2_FAULT = 163U, 
   DOUT_CBIT_SO_CCW3_FAULT = 164U, 
   DOUT_CBIT_SO_CCW4_FAULT = 165U, 
   DOUT_CBIT_SO_EN1_FAULT = 166U, 
   DOUT_CBIT_SO_EN2_FAULT = 167U, 
   DOUT_CBIT_SO_EN3_FAULT = 168U, 
   DOUT_CBIT_SO_EN4_FAULT = 169U, 
   DOUT_CBIT_G_CLCH1_FAULT = 170U, 
   DOUT_CBIT_G_CLCH2_FAULT = 171U, 
   DOUT_CBIT_G_CLCH3_FAULT = 172U, 
   DOUT_CBIT_G_CLCH4_FAULT = 173U, 
   DOUT_CBIT_S_CLCH1_FAULT = 174U, 
   DOUT_CBIT_S_CLCH2_FAULT = 175U, 
   DOUT_CBIT_S_CLCH3_FAULT = 176U, 
   DOUT_CBIT_S_CLCH4_FAULT = 177U, 
   DOUT_CBIT_SO_EXC1_FAULT = 178U, 
   DOUT_CBIT_SO_EXC2_FAULT = 179U, 
   DOUT_CBIT_SO_EXC3_FAULT = 180U, 
   DOUT_CBIT_SO_EXC4_FAULT = 181U, 
   DOUT_CBIT_G_EXT1_FAULT = 182U, 
   DOUT_CBIT_G_EXT2_FAULT = 183U, 
   DOUT_CBIT_G_EXT3_FAULT = 184U, 
   DOUT_CBIT_G_EXT4_FAULT = 185U, 
   DOUT_CBIT_S_EXT1_FAULT = 186U, 
   DOUT_CBIT_S_EXT2_FAULT = 187U, 
   DOUT_CBIT_S_EXT3_FAULT = 188U, 
   DOUT_CBIT_S_EXT4_FAULT = 189U, 
   DOUT_CBIT_G_RET1_FAULT = 190U, 
   DOUT_CBIT_G_RET2_FAULT = 191U, 
   DOUT_CBIT_G_RET3_FAULT = 192U, 
   DOUT_CBIT_G_RET4_FAULT = 193U, 
   DOUT_CBIT_S_RET1_FAULT = 194U, 
   DOUT_CBIT_S_RET2_FAULT = 195U, 
   DOUT_CBIT_S_RET3_FAULT = 196U, 
   DOUT_CBIT_S_RET4_FAULT = 197U, 
   DOUT_CBIT_OG_CH1_FAULT = 198U, 
   DOUT_CBIT_OG_CH2_FAULT = 199U, 
   DOUT_CBIT_OG_CH3_FAULT = 200U, 
   DOUT_CBIT_OG_CH4_FAULT = 201U, 
   DOUT_CBIT_OG_CH5_FAULT = 202U, 
   DOUT_CBIT_OG_CH6_FAULT = 203U, 
   DOUT_CBIT_OG_CH7_FAULT = 204U, 
   DOUT_CBIT_OG_CH8_FAULT = 205U, 
   DOUT_CBIT_OG_CH9_FAULT = 206U, 
   DOUT_CBIT_OG_CH10_FAULT = 207U, 
   DOUT_CBIT_OG_CH11_FAULT = 208U, 
   DOUT_CBIT_OG_CH12_FAULT = 209U, 
   DOUT_CBIT_OG_CH13_FAULT = 210U, 
   DOUT_CBIT_OG_CH14_FAULT = 211U, 
   DOUT_CBIT_OG_CH15_FAULT = 212U, 
   DOUT_CBIT_OG_CH16_FAULT = 213U, 
   DOUT_CBIT_SO_CH17_FAULT = 214U, 
   DOUT_CBIT_SO_CH18_FAULT = 215U, 
   DOUT_CBIT_SO_CH19_FAULT = 216U, 
   DOUT_CBIT_SO_CH20_FAULT = 217U, 
   DOUT_CBIT_SO_CH21_FAULT = 218U, 
   DOUT_CBIT_SO_CH22_FAULT = 219U, 
 
   DOUT_CBIT_CARD_1_OPEN_FAIL = 220U, 
   DOUT_CBIT_CARD_2_OPEN_FAIL = 221U, 
   DOUT_CBIT_MOD_1_INIT_FAIL = 222U, 
   DOUT_CBIT_MOD_2_INIT_FAIL = 223U 
} DOutCBITFailCode;

typedef enum
{
   PSU_CBIT_SUCCESS = 0U, 
   PSU_CBIT_INPUT_OVER_VOLTAGE_ALERT = 1U, 
   PSU_CBIT_INPUT_UNDER_VOLTAGE_ALERT = 2U, 
   PSU_CBIT_12V_OVER_VOLTAGE_ALERT = 3U, 
   PSU_CBIT_12V_UNDER_VOLTAGE_ALERT = 4U, 
   PSU_CBIT_5V_OVER_VOLTAGE_ALERT = 5U, 
   PSU_CBIT_5V_UNDER_VOLTAGE_ALERT = 6U, 
   PSU_CBIT_3V3_OVER_VOLTAGE_ALERT = 7U, 
   PSU_CBIT_3V3_UNDER_VOLTAGE_ALERT = 8U, 
   PSU_CBIT_N12_AUX_OVER_VOLTAGE_ALERT = 9U, 
   PSU_CBIT_N12_AUX_UNDER_VOLTAGE_ALERT = 10U, 
   PSU_CBIT_P12_AUX_OVER_VOLTAGE_ALERT = 11U, 
   PSU_CBIT_P12_AUX_UNDER_VOLTAGE_ALERT = 12U, 
   PSU_CBIT_3V3_AUX_OVER_VOLTAGE_ALERT = 13U, 
   PSU_CBIT_3V3_AUX_UNDER_VOLTAGE_ALERT = 14U, 
 
   PSU_CBIT_INPUT_OVER_CURRENT_ALERT = 15U, 
   PSU_CBIT_12V_OVER_CURRENT_ALERT = 16U, 
   PSU_CBIT_5V_OVER_CURRENT_ALERT = 17U, 
   PSU_CBIT_3V3_OVER_CURRENT_ALERT = 18U, 
   PSU_CBIT_N12_AUX_OVER_CURRENT_ALERT = 19U, 
   PSU_CBIT_P12_AUX_OVER_CURRENT_ALERT = 20U, 
   PSU_CBIT_3V3_AUX_OVER_CURRENT_ALERT = 21U, 
 
   PSU_CBIT_BOARD_OVER_TEMP_ALERT = 22U, 
   PSU_CBIT_12V_OVER_TEMP_ALERT = 23U, 
   PSU_CBIT_5V_OVER_TEMP_ALERT = 24U, 
   PSU_CBIT_3V3_OVER_TEMP_ALERT = 25U, 
   PSU_CBIT_N12_AUX_OVER_TEMP_ALERT = 26U, 
   PSU_CBIT_P12_AUX_OVER_TEMP_ALERT = 27U, 
   PSU_CBIT_3V3_AUX_OVER_TEMP_ALERT = 28U, 
   PSU_CBIT_PRIMARY_TRANSFORMER_OVER_TEMP_ALERT = 29U, 
 
   PSU_CBIT_COMM_ERR_ALERT = 30U, 
 
   PSU_CBIT_CARD_OPEN_FAIL = 31U, 
   PSU_CBIT_MOD_INIT_FAIL = 32U, 
   PSU_CBIT_FAIL = 33U 
} PsuCBITFailCode;

typedef enum
{
   PWM_PBIT_SUCCESS = 0U, 
   PWM_PBIT_INCOMPLETED = 1U, 
   PWM_PBIT_F_5V5 = 2U, 
   PWM_PBIT_IC_COMM_ERR_CH1 = 3U, 
   PWM_PBIT_IC_COMM_ERR_CH2 = 4U, 
   PWM_PBIT_IC_COMM_ERR_CH3 = 5U, 
   PWM_PBIT_IC_COMM_ERR_CH4 = 6U, 
   PWM_PBIT_CARD_OPEN_FAIL = 7U, 
   PWM_PBIT_MOD_INIT_FAIL = 8U 
} PwmPBITFailCode;

typedef enum
{
   PWM_CBIT_SUCCESS = 0U, 
   PWM_CBIT_DEV1_THERMAL_WARNING = 1U, 
   PWM_CBIT_DEV2_THERMAL_WARNING = 2U, 
   PWM_CBIT_DEV3_THERMAL_WARNING = 3U, 
   PWM_CBIT_DEV4_THERMAL_WARNING = 4U, 
   PWM_CBIT_DEV1_UNDERLOAD_ALERT = 5U, 
   PWM_CBIT_DEV2_UNDERLOAD_ALERT = 6U, 
   PWM_CBIT_DEV3_UNDERLOAD_ALERT = 7U, 
   PWM_CBIT_DEV4_UNDERLOAD_ALERT = 8U, 
   PWM_CBIT_DEV1_POWER_SUPPLY_FAIL = 9U, 
   PWM_CBIT_DEV2_POWER_SUPPLY_FAIL = 10U, 
   PWM_CBIT_DEV3_POWER_SUPPLY_FAIL = 11U, 
   PWM_CBIT_DEV4_POWER_SUPPLY_FAIL = 12U, 
   PWM_CBIT_DEV1_OVER_CURRENT_SHUTDOWN = 13U, 
   PWM_CBIT_DEV2_OVER_CURRENT_SHUTDOWN = 14U, 
   PWM_CBIT_DEV3_OVER_CURRENT_SHUTDOWN = 15U, 
   PWM_CBIT_DEV4_OVER_CURRENT_SHUTDOWN = 16U, 
   PWM_CBIT_DEV1_THERMAL_SHUTDOWN = 17U, 
   PWM_CBIT_DEV2_THERMAL_SHUTDOWN = 18U, 
   PWM_CBIT_DEV3_THERMAL_SHUTDOWN = 19U, 
   PWM_CBIT_DEV4_THERMAL_SHUTDOWN = 20U, 
   PWM_CBIT_UNDERLOAD_CH1 = 21U, 
   PWM_CBIT_UNDERLOAD_CH2 = 22U, 
   PWM_CBIT_UNDERLOAD_CH3 = 23U, 
   PWM_CBIT_UNDERLOAD_CH4 = 24U, 
   PWM_CBIT_OVERCURRENT_CH1 = 25U, 
   PWM_CBIT_OVERCURRENT_CH2 = 26U, 
   PWM_CBIT_OVERCURRENT_CH3 = 27U, 
   PWM_CBIT_OVERCURRENT_CH4 = 28U, 
   PWM_CBIT_NOT_RUN = 29U, 
   PWM_CBIT_5V5_FAULT = 30U, 
   PWM_CBIT_IC_COMM_ERR_CH1 = 31U, 
   PWM_CBIT_IVDC_FAULT_CH1 = 32U, 
   PWM_CBIT_IC_COMM_ERR_CH2 = 33U, 
   PWM_CBIT_IVDC_FAULT_CH2 = 34U, 
   PWM_CBIT_IC_COMM_ERR_CH3 = 35U, 
   PWM_CBIT_IVDC_FAULT_CH3 = 36U, 
   PWM_CBIT_IC_COMM_ERR_CH4 = 37U, 
   PWM_CBIT_IVDC_FAULT_CH4 = 38U, 
   PWM_CBIT_CARD_OPEN_FAIL = 39U, 
   PWM_CBIT_MOD_INIT_FAIL = 40U 
} PwmCBITFailCode;

typedef enum
{
   RVDT_PBIT_SUCCESS = 0U, 
   RVDT_PBIT_DONE = 1U, 
 
   RVDT_PBIT_DEV1_WRAM_FAIL = 2U, 
   RVDT_PBIT_DEV2_WRAM_FAIL = 3U, 
   RVDT_PBIT_DEV3_WRAM_FAIL = 4U, 
   RVDT_PBIT_DEV4_WRAM_FAIL = 5U, 
 
   RVDT_PBIT_DEV1_RAM_FAIL = 6U, 
   RVDT_PBIT_DEV2_RAM_FAIL = 7U, 
   RVDT_PBIT_DEV3_RAM_FAIL = 8U, 
   RVDT_PBIT_DEV4_RAM_FAIL = 9U, 
 
   RVDT_PBIT_DEV1_IC_COMM_FAIL = 10U, 
   RVDT_PBIT_DEV2_IC_COMM_FAIL = 11U, 
   RVDT_PBIT_DEV3_IC_COMM_FAIL = 12U, 
   RVDT_PBIT_DEV4_IC_COMM_FAIL = 13U, 
 
   RVDT_PBIT_BIT_DONE = 14U, 
   RVDT_PBIT_BIT_IC_COMM_FAIL = 15U, 
   RVDT_PBIT_BIT_RAM_FAIL = 16U, 
   RVDT_PBIT_BIT_WRAM_FAIL = 17U, 
   RVDT_PBIT_BIT_IOEXP_DONE = 18U, 
   RVDT_PBIT_BIT_IOEXP_IC_COMM_FAIL = 19U, 
 
   RVDT_PBIT_CARD_OPEN_FAIL = 20U, 
   RVDT_PBIT_MOD_INIT_FAIL = 21U 
} RvdtPBITFailCode;

typedef enum
{
   RVDT_CBIT_SUCCESS = 0U, 
   RVDT_CBIT_START = 1U, 
   RVDT_CBIT_PG_3V3 = 2U, 
   RVDT_CBIT_OVT = 3U, 
   RVDT_CBIT_F_3V3 = 4U, 
 
   RVDT_CBIT_PG_CH1 = 5U, 
   RVDT_CBIT_PG_CH2 = 6U, 
   RVDT_CBIT_PG_CH3 = 7U, 
   RVDT_CBIT_PG_CH4 = 8U, 
 
   RVDT_CBIT_F_3V3_BIT = 9U, 
   RVDT_CBIT_PG_BIT = 10U, 
 
   RVDT_CBIT_DEV1_IC_COMM_FAIL = 11U, 
   RVDT_CBIT_DEV2_IC_COMM_FAIL = 12U, 
   RVDT_CBIT_DEV3_IC_COMM_FAIL = 13U, 
   RVDT_CBIT_DEV4_IC_COMM_FAIL = 14U, 
 
   RVDT_CBIT_PG_3V3_BIT = 15U, 
   RVDT_CBIT_PG_15V_IO = 16U, 
   RVDT_CBIT_PG_15V_BIT = 17U, 
   RVDT_CBIT_F_3V3_ISO = 18U, 
   RVDT_CBIT_F_3V3_BIT_ISO = 19U, 
   RVDT_CBIT_UNDER_TEMP = 20U, 
 
   RVDT_CBIT_DEV1_S1_FAULT = 21U, 
   RVDT_CBIT_DEV2_S1_FAULT = 22U, 
   RVDT_CBIT_DEV3_S1_FAULT = 23U, 
   RVDT_CBIT_DEV4_S1_FAULT = 24U, 
 
   RVDT_CBIT_DEV1_S2_FAULT = 25U, 
   RVDT_CBIT_DEV2_S2_FAULT = 26U, 
   RVDT_CBIT_DEV3_S2_FAULT = 27U, 
   RVDT_CBIT_DEV4_S2_FAULT = 28U, 
 
   RVDT_CBIT_DEV1_EXC_FAULT = 29U, 
   RVDT_CBIT_DEV2_EXC_FAULT = 30U, 
   RVDT_CBIT_DEV3_EXC_FAULT = 31U, 
   RVDT_CBIT_DEV4_EXC_FAULT = 32U, 
 
   RVDT_CBIT_DEV1_REF_OVER_VOLTAGE_ALERT = 33U, 
   RVDT_CBIT_DEV1_REF_UNDER_VOLTAGE_ALERT = 34U, 
   RVDT_CBIT_DEV1_PRIMARY1_OVER_VOLTAGE_ALERT = 35U, 
   RVDT_CBIT_DEV1_PRIMARY1_UNDER_VOLTAGE_ALERT = 36U, 
   RVDT_CBIT_DEV1_PRIMARY1_OVER_CURRENT_ALERT = 37U, 
   RVDT_CBIT_DEV1_PRIMARY2_OVER_VOLTAGE_ALERT = 38U, 
   RVDT_CBIT_DEV1_PRIMARY2_UNDER_VOLTAGE_ALERT = 39U, 
   RVDT_CBIT_DEV1_PRIMARY2_OVER_CURRENT_ALERT = 40U, 
   RVDT_CBIT_DEV1_SECONDARY1_GAIN_OVER_VOLTAGE_ALERT = 41U, 
   RVDT_CBIT_DEV1_SECONDARY2_GAIN_OVER_VOLTAGE_ALERT = 42U, 
 
   RVDT_CBIT_DEV2_REF_OVER_VOLTAGE_ALERT = 43U, 
   RVDT_CBIT_DEV2_REF_UNDER_VOLTAGE_ALERT = 44U, 
   RVDT_CBIT_DEV2_PRIMARY1_OVER_VOLTAGE_ALERT = 45U, 
   RVDT_CBIT_DEV2_PRIMARY1_UNDER_VOLTAGE_ALERT = 46U, 
   RVDT_CBIT_DEV2_PRIMARY1_OVER_CURRENT_ALERT = 47U, 
   RVDT_CBIT_DEV2_PRIMARY2_OVER_VOLTAGE_ALERT = 48U, 
   RVDT_CBIT_DEV2_PRIMARY2_UNDER_VOLTAGE_ALERT = 49U, 
   RVDT_CBIT_DEV2_PRIMARY2_OVER_CURRENT_ALERT = 50U, 
   RVDT_CBIT_DEV2_SECONDARY1_GAIN_OVER_VOLTAGE_ALERT = 51U, 
   RVDT_CBIT_DEV2_SECONDARY2_GAIN_OVER_VOLTAGE_ALERT = 52U, 
 
   RVDT_CBIT_DEV3_REF_OVER_VOLTAGE_ALERT = 53U, 
   RVDT_CBIT_DEV3_REF_UNDER_VOLTAGE_ALERT = 54U, 
   RVDT_CBIT_DEV3_PRIMARY1_OVER_VOLTAGE_ALERT = 55U, 
   RVDT_CBIT_DEV3_PRIMARY1_UNDER_VOLTAGE_ALERT = 56U, 
   RVDT_CBIT_DEV3_PRIMARY1_OVER_CURRENT_ALERT = 57U, 
   RVDT_CBIT_DEV3_PRIMARY2_OVER_VOLTAGE_ALERT = 58U, 
   RVDT_CBIT_DEV3_PRIMARY2_UNDER_VOLTAGE_ALERT = 59U, 
   RVDT_CBIT_DEV3_PRIMARY2_OVER_CURRENT_ALERT = 60U, 
   RVDT_CBIT_DEV3_SECONDARY1_GAIN_OVER_VOLTAGE_ALERT = 61U, 
   RVDT_CBIT_DEV3_SECONDARY2_GAIN_OVER_VOLTAGE_ALERT = 62U, 
 
   RVDT_CBIT_DEV4_REF_OVER_VOLTAGE_ALERT = 63U, 
   RVDT_CBIT_DEV4_REF_UNDER_VOLTAGE_ALERT = 64U, 
   RVDT_CBIT_DEV4_PRIMARY1_OVER_VOLTAGE_ALERT = 65U, 
   RVDT_CBIT_DEV4_PRIMARY1_UNDER_VOLTAGE_ALERT = 66U, 
   RVDT_CBIT_DEV4_PRIMARY1_OVER_CURRENT_ALERT = 67U, 
   RVDT_CBIT_DEV4_PRIMARY2_OVER_VOLTAGE_ALERT = 68U, 
   RVDT_CBIT_DEV4_PRIMARY2_UNDER_VOLTAGE_ALERT = 69U, 
   RVDT_CBIT_DEV4_PRIMARY2_OVER_CURRENT_ALERT = 70U, 
   RVDT_CBIT_DEV4_SECONDARY1_GAIN_OVER_VOLTAGE_ALERT = 71U, 
   RVDT_CBIT_DEV4_SECONDARY2_GAIN_OVER_VOLTAGE_ALERT = 72U, 
 
   RVDT_CBIT_BIT_IC_COMM_FAIL = 73U, 
   RVDT_CBIT_BIT_IOEXP_IC_COMM_FAIL = 74U, 
 
   RVDT_CBIT_CARD_OPEN_FAIL = 75U, 
   RVDT_CBIT_MOD_INIT_FAIL = 76U 
} RvdtCBITFailCode;

typedef struct
{
   UInt32 failCount; 
   MfbPBITFailCode failCode[MOD_HSB_COMMON_MFB_PBIT_MAX_FAIL_COUNT]; 
} MfbPBITFailResult;

typedef struct
{
   UInt32 failCount; 
   MfbCBITFailCode failCode[MOD_HSB_COMMON_MFB_CBIT_MAX_FAIL_COUNT]; 
} MfbCBITFailResult;

typedef struct
{
   UInt32 failCount; 
   PsuCBITFailCode failCode[MOD_HSB_COMMON_PSU_CBIT_MAX_FAIL_COUNT]; 
} PsuCBITFailResult;

typedef struct
{
   UInt32 failCount; 
   AInPBITFailCode failCode[MOD_HSB_COMMON_AIN_PBIT_MAX_FAIL_COUNT]; 
} AInPBITFailResult;

typedef struct
{
   UInt32 failCount; 
   AInCBITFailCode failCode[MOD_HSB_COMMON_AIN_CBIT_MAX_FAIL_COUNT]; 
} AInCBITFailResult;

typedef struct
{
   UInt32 failCount; 
   A429PBITFailCode failCode[MOD_HSB_COMMON_A429_PBIT_MAX_FAIL_COUNT]; 
} A429PBITFailResult;

typedef struct
{
   UInt32 failCount; 
   A429CBITFailCode failCode[MOD_HSB_COMMON_A429_CBIT_MAX_FAIL_COUNT]; 
} A429CBITFailResult;

typedef struct
{
   UInt32 failCount; 
   DInPBITFailCode failCode[MOD_HSB_COMMON_DIN_PBIT_MAX_FAIL_COUNT]; 
} DInPBITFailResult;

typedef struct
{
   UInt32 failCount; 
   DInCBITFailCode failCode[MOD_HSB_COMMON_DIN_CBIT_MAX_FAIL_COUNT]; 
} DInCBITFailResult;

typedef struct
{
   UInt32 failCount; 
   DOutPBITFailCode failCode[MOD_HSB_COMMON_DOUT_PBIT_MAX_FAIL_COUNT]; 
} DOutPBITFailResult;

typedef struct
{
   UInt32 failCount; 
   DOutCBITFailCode failCode[MOD_HSB_COMMON_DOUT_CBIT_MAX_FAIL_COUNT]; 
} DOutCBITFailResult;

typedef struct
{
   UInt32 failCount; 
   PwmPBITFailCode failCode[MOD_HSB_COMMON_PWM_PBIT_MAX_FAIL_COUNT]; 
} PwmPBITFailResult;

typedef struct
{
   UInt32 failCount; 
   PwmCBITFailCode failCode[MOD_HSB_COMMON_PWM_CBIT_MAX_FAIL_COUNT]; 
} PwmCBITFailResult;

typedef struct
{
   UInt32 failCount; 
   RvdtPBITFailCode failCode[MOD_HSB_COMMON_RVDT_PBIT_MAX_FAIL_COUNT]; 
} RvdtPBITFailResult;

typedef struct
{
   UInt32 failCount; 
   RvdtCBITFailCode failCode[MOD_HSB_COMMON_RVDT_CBIT_MAX_FAIL_COUNT]; 
} RvdtCBITFailResult;
 
#endif // MOD_HSB_COMMON_H