mmap_analog_in_8h_source.html

/*

 * Copyright (c) 2025, TUSAS Malaysia

 * All rights reserved.

 * This file contains proprietary information. This

 * file shall not be duplicated, used, modified,

 * or disclosed in whole or in part without

 * the express written consent of TUSAS.

 */


#ifndef INCLUDED_MMAP_ANALOG_IN_H

#define INCLUDED_MMAP_ANALOG_IN_H


// =========================================================================


// mfb - memory map offset for ADC

#define MMAP_ADC_OFFSET (0x3000U)


// =========================================================================


// channel offset

#define MMAP_ADC_CH_OFFSET_GAP (0x0004U)


// =========================================================================


// memory map offset list

#define MMAP_ADC_IN_RG_BANK_BASE (0x0000U)

#define MMAP_ADC_IN_RG_BANK0     (0x0000U)

#define MMAP_ADC_IN_RG_BANK1     (0x0004U)

#define MMAP_ADC_SAMPLING_RATE   (0x0008U)

#define MMAP_ADC_CH_ENABLE       (0x000CU)


#define MMAP_ADC_CH_STATE            (0x0100U)

#define MMAP_ADC_PBIT_GEN_STATUS     (0x0104U)

#define MMAP_ADC_PBIT_OVP_STATUS     (0x0108U)

#define MMAP_ADC_PBIT_IVR_ERR_STATUS (0x010CU)

#define MMAP_ADC_CBIT_GEN_STATUS     (0x0110U)

#define MMAP_ADC_CBIT_OVP_STATUS     (0x0114U)

#define MMAP_ADC_CBIT_IVR_ERR_STATUS (0x0118U)

#define MMAP_ADC_TEMP_5V             (0x011CU)

#define MMAP_ADC_TEMP_10V            (0x0120U)


#define MMAP_ADC_RD_BASE_ADDR (0x0200U)


// =========================================================================


// Bit position for PBIT and CBIT

#define MMAP_ADC_POS_PBIT_INCOMPLETED          (0U)

#define MMAP_ADC_POS_PBIT_F_3V3                (8U)

#define MMAP_ADC_POS_PBIT_F_5V                 (9U)

#define MMAP_ADC_POS_PBIT_F_15V                (10U)

#define MMAP_ADC_POS_PBIT_UT_BANK0             (11U)

#define MMAP_ADC_POS_PBIT_OT_BANK0             (12U)

#define MMAP_ADC_POS_PBIT_UT_BANK1             (13U)

#define MMAP_ADC_POS_PBIT_OT_BANK1             (14U)

#define MMAP_ADC_POS_PBIT_IC_COMM_ERR_CH1      (16U)

#define MMAP_ADC_POS_PBIT_IC_COMM_ERR_CH2      (17U)

#define MMAP_ADC_POS_PBIT_IC_COMM_ERR_CH3      (18U)

#define MMAP_ADC_POS_PBIT_IC_COMM_ERR_CH4      (19U)

#define MMAP_ADC_POS_PBIT_IC_COMM_ERR_CH5      (20U)

#define MMAP_ADC_POS_PBIT_IC_COMM_ERR_CH6      (21U)

#define MMAP_ADC_POS_PBIT_IC_COMM_ERR_CH7      (22U)

#define MMAP_ADC_POS_PBIT_IC_COMM_ERR_CH8      (23U)

#define MMAP_ADC_POS_PBIT_IC_COMM_ERR_LB_BANK0 (24U)

#define MMAP_ADC_POS_PBIT_IC_COMM_ERR_LB_BANK1 (25U)


#define MMAP_ADC_POS_PBIT_OVP_CH1 (0U)

#define MMAP_ADC_POS_PBIT_OVP_CH2 (1U)

#define MMAP_ADC_POS_PBIT_OVP_CH3 (2U)

#define MMAP_ADC_POS_PBIT_OVP_CH4 (3U)

#define MMAP_ADC_POS_PBIT_OVP_CH5 (4U)

#define MMAP_ADC_POS_PBIT_OVP_CH6 (5U)

#define MMAP_ADC_POS_PBIT_OVP_CH7 (6U)

#define MMAP_ADC_POS_PBIT_OVP_CH8 (7U)


#define MMAP_ADC_POS_PBIT_IVR_ERR_CH1 (0U)

#define MMAP_ADC_POS_PBIT_IVR_ERR_CH2 (1U)

#define MMAP_ADC_POS_PBIT_IVR_ERR_CH3 (2U)

#define MMAP_ADC_POS_PBIT_IVR_ERR_CH4 (3U)

#define MMAP_ADC_POS_PBIT_IVR_ERR_CH5 (4U)

#define MMAP_ADC_POS_PBIT_IVR_ERR_CH6 (5U)

#define MMAP_ADC_POS_PBIT_IVR_ERR_CH7 (6U)

#define MMAP_ADC_POS_PBIT_IVR_ERR_CH8 (7U)


#define MMAP_ADC_POS_PBIT_CARD_OPEN_FAIL (34U)

#define MMAP_ADC_POS_PBIT_MOD_INIT_FAIL  (35U)

#define MMAP_ADC_POS_PBIT_FAIL           (36U)


#define MMAP_ADC_POS_CBIT_NOT_RUN              (0U)

#define MMAP_ADC_POS_CBIT_F_3V3                (8U)

#define MMAP_ADC_POS_CBIT_F_5V5                (9U)

#define MMAP_ADC_POS_CBIT_F_15V                (10U)

#define MMAP_ADC_POS_CBIT_UT_BANK0             (11U)

#define MMAP_ADC_POS_CBIT_OT_BANK0             (12U)

#define MMAP_ADC_POS_CBIT_UT_BANK1             (13U)

#define MMAP_ADC_POS_CBIT_OT_BANK1             (14U)

#define MMAP_ADC_POS_CBIT_IC_COMM_ERR_CH1      (16U)

#define MMAP_ADC_POS_CBIT_IC_COMM_ERR_CH2      (17U)

#define MMAP_ADC_POS_CBIT_IC_COMM_ERR_CH3      (18U)

#define MMAP_ADC_POS_CBIT_IC_COMM_ERR_CH4      (19U)

#define MMAP_ADC_POS_CBIT_IC_COMM_ERR_CH5      (20U)

#define MMAP_ADC_POS_CBIT_IC_COMM_ERR_CH6      (21U)

#define MMAP_ADC_POS_CBIT_IC_COMM_ERR_CH7      (22U)

#define MMAP_ADC_POS_CBIT_IC_COMM_ERR_CH8      (23U)

#define MMAP_ADC_POS_CBIT_IC_COMM_ERR_LB_BANK0 (24U)

#define MMAP_ADC_POS_CBIT_IC_COMM_ERR_LB_BANK1 (25U)


#define MMAP_ADC_POS_CBIT_OVP_CH1 (0U)

#define MMAP_ADC_POS_CBIT_OVP_CH2 (1U)

#define MMAP_ADC_POS_CBIT_OVP_CH3 (2U)

#define MMAP_ADC_POS_CBIT_OVP_CH4 (3U)

#define MMAP_ADC_POS_CBIT_OVP_CH5 (4U)

#define MMAP_ADC_POS_CBIT_OVP_CH6 (5U)

#define MMAP_ADC_POS_CBIT_OVP_CH7 (6U)

#define MMAP_ADC_POS_CBIT_OVP_CH8 (7U)


#define MMAP_ADC_POS_CBIT_IVR_ERR_CH1 (0U)

#define MMAP_ADC_POS_CBIT_IVR_ERR_CH2 (1U)

#define MMAP_ADC_POS_CBIT_IVR_ERR_CH3 (2U)

#define MMAP_ADC_POS_CBIT_IVR_ERR_CH4 (3U)

#define MMAP_ADC_POS_CBIT_IVR_ERR_CH5 (4U)

#define MMAP_ADC_POS_CBIT_IVR_ERR_CH6 (5U)

#define MMAP_ADC_POS_CBIT_IVR_ERR_CH7 (6U)

#define MMAP_ADC_POS_CBIT_IVR_ERR_CH8 (7U)


#define MMAP_ADC_POS_CBIT_CARD_OPEN_FAIL (34U)

#define MMAP_ADC_POS_CBIT_MOD_INIT_FAIL  (35U)

#define MMAP_ADC_POS_CBIT_FAIL           (36U)


// =========================================================================


// memory map constrains

#define MMAP_ADC_TEMP_LSB   (0.005F)

#define MMAP_ADC_POS_CH_NUM (1U)


// =========================================================================


#endif // INCLUDED_MMAP_ANALOG_IN_H