HFCC-01 Low-Level Software (LLSW) Rel_6802_HFCC-01-RP-CSAR-CB
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Low-Level Device Drivers for Core system initialization, NVSRAM mapping, and resets.

Collaboration diagram for System & Core Drivers:
System & Core Drivers Node2 Drivers - Low-Level Device Drivers Node1 System & Core Drivers Node2->Node1

Low-Level Device Drivers for Core system initialization, NVSRAM mapping, and resets.

Core System & NVSRAM Driver Architecture (core.h)

The Core System driver manages chassis-level supervisor logic and non-volatile memory:

  • Chassis Controller (mmapCore.h, base 0x0000): Master FPGA configuration registers, board soft reset, hardware watchdog kick registers, and board status flags.
  • NVSRAM Memory Controller (coreNvsramMap.h, base 0x0000): High-reliability battery-backed SRAM access for flight history, PBIT/CBIT fault bitmasks, and factory calibration tables.