Drivers - Low-Level Device Drivers

Direct hardware interface drivers managing PCIe MMIO register access via FPGA AXI bridge. More...

Collaboration diagram for Drivers - Low-Level Device Drivers:

Topics
	Communication Bus Drivers
	Low-Level Device Drivers for ARINC 429 communication interface.
	Analog & Discrete I/O Drivers
	Low-Level Device Drivers for Analog Input ADC, Discrete Input/Output, PWM, and RVDT.
	Power Supply Unit Drivers
	Low-Level Device Drivers for PSU rail monitoring, telemetry, and temperature sensors.
	System & Core Drivers
	Low-Level Device Drivers for Core system initialization, NVSRAM mapping, and resets.
	Interface Layer Drivers
	Inter-driver shared memory mapping and top-level interface abstractions.

Detailed Description

Direct hardware interface drivers managing PCIe MMIO register access via FPGA AXI bridge.

Low-Level Device Driver (LLDD) Architecture Overview

The Low-Level Device Driver (LLDD) layer sits at the base of the HFCC-01 software stack, providing physical access to FPGA logic registers, peripheral controllers, and hardware transducers across the PCIe Memory-Mapped I/O (MMIO) bus aperture.

Core Driver Responsibilities

1. Direct MMIO Register Manipulation: Performing atomic 32-bit/16-bit reads and writes to peripheral control, status, and data FIFO registers.
2. Hardware Timing & Sequencer Synchronization: Executing microsecond-precision strobe pulses, ADC settling delays, and demodulator filter phase alignments.
3. Calibration Polynomial Application: Applying factory offset, gain, and non-linearity correction polynomials loaded from non-volatile memory (coreNvsramMap.h).
4. Hardware Diagnostic Interrogation: Interrogating low-level fault status registers, FIFO overflow flags, and power rail telemetry sensors.

Driver Category Overview

• Communication Bus Drivers: ARINC 429 protocol controller (a429.h).
• Analog & Discrete I/O Drivers: ADC sensing, discrete switching, PWM, and RVDT demodulation.
• Power Supply Unit Drivers: Multi-rail power monitoring and thermal telemetry (psu.h).
• System & Core Drivers: Chassis reset, NVSRAM management, and core FPGA control (core.h).
• Interface Layer Drivers: Inter-driver shared memory and IPC bridges (interDrv.h).