HFCC-01 Low-Level Software (LLSW) Rel_6802_HFCC-01-RP-CSAR-CB
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inter.c File Reference
#include "pciConfig.h"
#include "bspExport.h"
#include "pcieUtils.h"
#include "memoryOper.h"
#include "inter.h"
Include dependency graph for inter.c:
inter.c Node1 inter.c Node2 pciConfig.h Node1->Node2 Node3 bspExport.h Node1->Node3 Node4 pcieUtils.h Node1->Node4 Node5 memoryOper.h Node1->Node5 Node6 inter.h Node1->Node6 Node7 fswCommonTypes.h Node6->Node7

Macros

#define INTER_PEX_DEV_2   (0x01)
#define INTER_MFB1_DEV_INDEX   (0x00)
#define INTER_MFB2_DEV_INDEX   (0x01)
#define INTER_PEX_CFG_READY_VALUE   (0x00)
#define INTER_MFB1_VENDOR_ID   (0x701310EE)
#define INTER_MFB2_VENDOR_ID   (0x701410EE)

Functions

void pci_init_hook (StatusInfo *mrStatus)
 pci_init_hook.

Detailed Description

Author
Ramza Anuar ramza.nosp@m..anu.nosp@m.ar@tu.nosp@m.sas..nosp@m.my

Interface File

Macro Definition Documentation

◆ INTER_MFB1_DEV_INDEX

#define INTER_MFB1_DEV_INDEX   (0x00)

◆ INTER_MFB1_VENDOR_ID

#define INTER_MFB1_VENDOR_ID   (0x701310EE)

◆ INTER_MFB2_DEV_INDEX

#define INTER_MFB2_DEV_INDEX   (0x01)

◆ INTER_MFB2_VENDOR_ID

#define INTER_MFB2_VENDOR_ID   (0x701410EE)

◆ INTER_PEX_CFG_READY_VALUE

#define INTER_PEX_CFG_READY_VALUE   (0x00)

◆ INTER_PEX_DEV_2

#define INTER_PEX_DEV_2   (0x01)

Function Documentation

◆ pci_init_hook()

void pci_init_hook ( StatusInfo * mrStatus)

pci_init_hook.

Initializes the PCI device drivers for the current CPU and updates the status register for MFB1 and MFB2 devices. It also retrieves the PCI device driver for specified slots.

Parameters
[in]mrStatusA pointer to the StatusInfo structure where the MFB1 and MFB2 status values will be set.
Returns
void - This function does not return any value.

Low-Level Software Requirements (LLR)

Low-Level Requirement Specification: pci_init_hook

Requirement ID Parent HLR ID Detailed Low-Level Requirement Statement (EARS Format) Software Unit Reference Verification Method Status
LLR_INTER_PCI_INIT_HOOK_01 HLR_IO_36773 WHEN the pointer mrStatus is NULL (invalid), the pci_init_hook() function SHALL abort processing and return immediately without modifying hardware registers. inter.c:pci_init_hook() Test Closed
LLR_INTER_PCI_INIT_HOOK_02 HLR_IO_36773 WHEN the pointer mrStatus is valid, the pci_init_hook() function SHALL zero-initialize struct mrStatus and enable PCIe memory space and bus mastering on all configured PCI switch devices. inter.c:pci_init_hook() Test Closed
LLR_INTER_PCI_INIT_HOOK_03 HLR_IO_36773 WHEN PCIe command registers are configured, the pci_init_hook() function SHALL read vendor identifiers and configuration ready registers for MFB1 and MFB2 devices. inter.c:pci_init_hook() Test Closed
LLR_INTER_PCI_INIT_HOOK_04 HLR_IO_36773 WHEN mrStatus->cfgReady1 is equal to INTER_PEX_CFG_READY_VALUE and mrStatus->vendorId1 matches INTER_MFB1_VENDOR_ID, the pci_init_hook() function SHALL assert MFB1 PCIe readiness by setting mrStatus->mfb1Status to 1. inter.c:pci_init_hook() Test Closed
LLR_INTER_PCI_INIT_HOOK_05 HLR_IO_36773 WHEN mrStatus->cfgReady2 is equal to INTER_PEX_CFG_READY_VALUE and mrStatus->vendorId2 matches INTER_MFB2_VENDOR_ID, the pci_init_hook() function SHALL assert MFB2 PCIe readiness by setting mrStatus->mfb2Status to 1. inter.c:pci_init_hook() Test Closed

Control Coupling Diagram (CCD)

ControlCouplingStructureChart Caller pci_init_hook() [Low-Level Device Drivers] Target memoryOper_set() [Low-Level Driver Helper] Caller:s->Target:n l_t0->l_b0   channelNum (Flag) l_t1->l_b1   opMode (Flag) r_b0->r_t0   statusCode (void)
Control Coupling Structure Chart

Data Coupling Diagram (DCD)

DataCouplingStructureChart Caller pci_init_hook() [Low-Level Device Drivers] Target memoryOper_set() [Low-Level Driver Helper] Caller:s->Target:n l_t0->l_b0   dataBufferPtr (Payload) r_b0->r_t0   *mrStatus (Output Data)
Data Coupling Structure Chart

Control Flow Diagram (CFD)

cfd_pci_init_hook start Entry: pci_init_hook() guard_1 LLR_01: Guard Check Is the pointer `mrStatus` is NULL (invalid)? start->guard_1 err_exit_1 LLR_01 Error Exit abort processing and return `error status` guard_1->err_exit_1 YES (TRUE) guard_2 LLR_02: Guard Check Is `INTER_PEX_CFG_READY_VALUE` is equal to `mrStatus`->cfgReady1? guard_1->guard_2 err_exit_2 LLR_02 Error Exit execute conditional operational branch guard_2->err_exit_2 YES (TRUE) guard_3 LLR_03: Guard Check Is `INTER_PEX_CFG_READY_VALUE` is equal to `mrStatus`->cfgReady2? guard_2->guard_3 err_exit_3 LLR_03 Error Exit execute conditional operational branch guard_3->err_exit_3 YES (TRUE) act_4 LLR_04: Action Step invoke routine `memoryOper_set()` to execute target subsystem hardware operation guard_3->act_4 NO (FALSE) act_5 LLR_05: Action Step invoke routine `PCIE_CONFIG_BASE()` to execute target subsystem hardware operation act_4->act_5 act_6 LLR_06: Action Step invoke routine `pcieUtils_busRead2B()` to execute target subsystem hardware operation act_5->act_6 act_7 LLR_07: Action Step invoke routine `pcieUtils_busWrite2B()` to execute target subsystem hardware operation act_6->act_7 act_8 LLR_08: Action Step invoke routine `pcieUtils_busRead4B()` to execute target subsystem hardware operation act_7->act_8 success_exit LLR_09: Final Exit return `the computed result` act_8->success_exit
Control Flow Diagram

Data Flow Diagram (DFD)

dfd_pci_init_hook in_store Input Data Sources & Parameters • Function Inputs & Subsystem State proc_1 LLR_01: Data Validation Check • Evaluate Parameter / State: mrStatus in_store->proc_1 Validated Input Data proc_2 LLR_02: Data Validation Check • Evaluate Parameter / State: INTER_PEX_CFG_READY_VALUE proc_1->proc_2 Validated Input Data proc_3 LLR_03: Data Validation Check • Evaluate Parameter / State: INTER_PEX_CFG_READY_VALUE proc_2->proc_3 Validated Input Data proc_4 LLR_04: Data Payload Transformation • Process payload via memoryOper_set() proc_3->proc_4 Data Payload (memoryOper_set) proc_5 LLR_05: Data Payload Transformation • Process payload via PCIE_CONFIG_BASE() proc_4->proc_5 Data Payload (PCIE_CONFIG_BASE) proc_6 LLR_06: Data Payload Transformation • Process payload via pcieUtils_busRead2B() proc_5->proc_6 Data Payload (pcieUtils_busRead2B) proc_7 LLR_07: Data Payload Transformation • Process payload via pcieUtils_busWrite2B() proc_6->proc_7 Data Payload (pcieUtils_busWrite2B) proc_8 LLR_08: Data Payload Transformation • Process payload via pcieUtils_busRead4B() proc_7->proc_8 Data Payload (pcieUtils_busRead4B) proc_9 LLR_09: Status Output Packaging • Format Return Payload: void proc_8->proc_9 Final Output Data out_sink Output Data Sinks & Status Return • mrStatus (StatusInfo) proc_9->out_sink Output Data & Status Code
Data Flow Diagram
Here is the call graph for this function:
pci_init_hook Node1 pci_init_hook Node1->Node1
Here is the caller graph for this function:
pci_init_hook Node1 pci_init_hook Node1->Node1