Communication Bus Drivers

Low-Level Device Drivers for ARINC 429 communication interface.

Collaboration diagram for Communication Bus Drivers:

Low-Level Device Drivers for ARINC 429 communication interface.

ARINC 429 Driver Architecture (a429.h)

The ARINC 429 driver communicates directly with the multi-channel ARINC 429 FPGA core:

• Register Base Offsets: 0x5000 (Control/Status) and 0x1000 (Channel Registers) per mmapA429.h.
• Tx/Rx FIFOs: Manages 32-word hardware transmission and reception circular FIFO buffers.
• Label Filtering: Configures 256-bit hardware label acceptance filters and SDI match registers.
• Baud Rate Clocking: Supports independent per-channel clock prescaler configuration for 12.5 kbps (Low Speed) and 100 kbps (High Speed) avionics bus operations.