- Generated by
1.18.0
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HFCC-01 Low-Level Software (LLSW) Rel_6802_HFCC-01-RP-CSAR-CB
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Go to the source code of this file.
Memory Map for ARINC429
| #define MMAP_A429_CBIT_DATA (0x01F4U) |
| #define MMAP_A429_CBIT_STAT (0x01F0U) |
| #define MMAP_A429_CH_GAP (0x04U) |
| #define MMAP_A429_FIFO_COUNT_CH_GAP (0x08U) |
| #define MMAP_A429_FIFO_MESSAGE_CH_GAP (0x08U) |
| #define MMAP_A429_LABEL_FILTER_BASE (0x00C4U) |
| #define MMAP_A429_LABEL_FILTER_CH_GAP (0x20U) |
| #define MMAP_A429_MCR (0x0000U) |
| #define MMAP_A429_MCR_AFLIP_BITMASK (0x08U) |
| #define MMAP_A429_MCR_RX_BITMASK (0x80U) |
| #define MMAP_A429_MCR_TX7OPT_BITMASK (0x02U) |
| #define MMAP_A429_MCR_TX_BITMASK (0x40U) |
| #define MMAP_A429_MCR_TXDL256_BITMASK (0x01U) |
| #define MMAP_A429_MCR_TXMSK_BITMASK (0x04U) |
| #define MMAP_A429_OFFSET (0x5000U) |
| #define MMAP_A429_PBIT_STAT (0x01ECU) |
| #define MMAP_A429_POS_CBIT_COMM_ERR (8U) |
| #define MMAP_A429_POS_CBIT_IC_NOT_READY (7U) |
| #define MMAP_A429_POS_CBIT_MISMATCH_RXCH1 (4U) |
| #define MMAP_A429_POS_CBIT_MISMATCH_RXCH2 (5U) |
| #define MMAP_A429_POS_CBIT_MISMATCH_RXCH3 (6U) |
| #define MMAP_A429_POS_CBIT_MISMATCH_RXCH4 (7U) |
| #define MMAP_A429_POS_CBIT_MISMATCH_RXCH5 (8U) |
| #define MMAP_A429_POS_CBIT_MISMATCH_RXCH6 (9U) |
| #define MMAP_A429_POS_CBIT_MISMATCH_RXCH7 (10U) |
| #define MMAP_A429_POS_CBIT_MISMATCH_TXCH1 (0U) |
| #define MMAP_A429_POS_CBIT_MISMATCH_TXCH2 (1U) |
| #define MMAP_A429_POS_CBIT_MISMATCH_TXCH3 (2U) |
| #define MMAP_A429_POS_CBIT_MISMATCH_TXCH4 (3U) |
| #define MMAP_A429_POS_CBIT_NOT_DONE (0U) |
| #define MMAP_A429_POS_CBIT_OVT (6U) |
| #define MMAP_A429_POS_CBIT_PWR_FAULT_3V3 (1U) |
| #define MMAP_A429_POS_CBIT_PWR_FAULT_BIT (2U) |
| #define MMAP_A429_POS_CBIT_PWR_FAULT_ISO (3U) |
| #define MMAP_A429_POS_CBIT_PWR_FAULT_TX_DRV (4U) |
| #define MMAP_A429_POS_CBIT_RECEIVE_RXCH1 (15U) |
| #define MMAP_A429_POS_CBIT_RECEIVE_RXCH2 (16U) |
| #define MMAP_A429_POS_CBIT_RECEIVE_RXCH3 (17U) |
| #define MMAP_A429_POS_CBIT_RECEIVE_RXCH4 (18U) |
| #define MMAP_A429_POS_CBIT_RECEIVE_RXCH5 (19U) |
| #define MMAP_A429_POS_CBIT_RECEIVE_RXCH6 (20U) |
| #define MMAP_A429_POS_CBIT_RECEIVE_RXCH7 (21U) |
| #define MMAP_A429_POS_CBIT_RECEIVE_TXCH1 (11U) |
| #define MMAP_A429_POS_CBIT_RECEIVE_TXCH2 (12U) |
| #define MMAP_A429_POS_CBIT_RECEIVE_TXCH3 (13U) |
| #define MMAP_A429_POS_CBIT_RECEIVE_TXCH4 (14U) |
| #define MMAP_A429_POS_CBIT_RX_LB_COMM_ERR (12U) |
| #define MMAP_A429_POS_CBIT_RX_LB_NOT_READY (11U) |
| #define MMAP_A429_POS_CBIT_TX_LB_COMM_ERR (10U) |
| #define MMAP_A429_POS_CBIT_TX_LB_NOT_READY (9U) |
| #define MMAP_A429_POS_CBIT_UT (5U) |
| #define MMAP_A429_POS_FLAG_FIFO_ALMOST_FULL (1U) |
| #define MMAP_A429_POS_FLAG_FIFO_EMPTY (0U) |
| #define MMAP_A429_POS_FLAG_FIFO_FULL (2U) |
| #define MMAP_A429_POS_PBIT_BIST_ERR (3U) |
| #define MMAP_A429_POS_PBIT_COMM_ERR (2U) |
| #define MMAP_A429_POS_PBIT_IC_NOT_READY (1U) |
| #define MMAP_A429_POS_PBIT_LOOPBACK_RX_CH1 (8U) |
| #define MMAP_A429_POS_PBIT_LOOPBACK_RX_CH2 (9U) |
| #define MMAP_A429_POS_PBIT_LOOPBACK_RX_CH3 (10U) |
| #define MMAP_A429_POS_PBIT_LOOPBACK_RX_CH4 (11U) |
| #define MMAP_A429_POS_PBIT_LOOPBACK_RX_CH5 (12U) |
| #define MMAP_A429_POS_PBIT_LOOPBACK_RX_CH6 (13U) |
| #define MMAP_A429_POS_PBIT_LOOPBACK_RX_CH7 (14U) |
| #define MMAP_A429_POS_PBIT_LOOPBACK_TX_CH1 (4U) |
| #define MMAP_A429_POS_PBIT_LOOPBACK_TX_CH2 (5U) |
| #define MMAP_A429_POS_PBIT_LOOPBACK_TX_CH3 (6U) |
| #define MMAP_A429_POS_PBIT_LOOPBACK_TX_CH4 (7U) |
| #define MMAP_A429_POS_PBIT_NOT_DONE (15U) |
| #define MMAP_A429_POS_PBIT_PWR_FAULT (0U) |
| #define MMAP_A429_POS_PBIT_RAM_BIST_FAIL (17U) |
| #define MMAP_A429_POS_PBIT_RAM_BIST_LOWERBIT_FAIL (19U) |
| #define MMAP_A429_POS_PBIT_RAM_BIST_NOT_DONE (16U) |
| #define MMAP_A429_POS_PBIT_RAM_BIST_UPPERBIT_FAIL (18U) |
| #define MMAP_A429_RESET_MODULE (0x0028U) |
| #define MMAP_A429_RX_CR_BASE (0x0004U) |
| #define MMAP_A429_RX_CR_POS_ENABLE (7U) |
| #define MMAP_A429_RX_CR_POS_ENABLE_SDI (4U) |
| #define MMAP_A429_RX_CR_POS_PARITY (5U) |
| #define MMAP_A429_RX_CR_POS_SD10 (3U) |
| #define MMAP_A429_RX_CR_POS_SD9 (2U) |
| #define MMAP_A429_RX_CR_POS_SPEED (1U) |
| #define MMAP_A429_RX_ENABLE_FIFO_BITMASK (0x10U) |
| #define MMAP_A429_RX_ENABLE_LABEL_FILTER (0x20U) |
| #define MMAP_A429_RX_ENABLE_RAM_BITMASK (0x08U) |
| #define MMAP_A429_RX_FIFO_COUNT_BASE (0x023CU) |
| #define MMAP_A429_RX_FIFO_DISABLE_FLAG (0U) |
| #define MMAP_A429_RX_FIFO_ENABLE_FLAG (0x10U) |
| #define MMAP_A429_RX_FIFO_MESSAGE_BASE (0x0240U) |
| #define MMAP_A429_RX_FLAG_BASE (0x0044U) |
| #define MMAP_A429_RX_FLAG_FIFO_ALMOST_FULL_BITMASK (0x02U) |
| #define MMAP_A429_RX_FLAG_FIFO_EMPTY_BITMASK (0x01U) |
| #define MMAP_A429_RX_FLAG_FIFO_FULL_BITMASK (0x04U) |
| #define MMAP_A429_RX_RAM_BASE (0x01FCU) |
| #define MMAP_A429_SCH_OFFSET (0x1000U) |
| #define MMAP_A429_SEGMENT_GAP (0x04U) |
| #define MMAP_A429_SW_RESET (0x034CU) |
| #define MMAP_A429_TEMP (0x01F8U) |
| #define MMAP_A429_TEMP_LSB (0.005F) |
| #define MMAP_A429_TX_CR_BASE (0X0084U) |
| #define MMAP_A429_TX_CR_POS_ENABLE (2U) |
| #define MMAP_A429_TX_CR_POS_ENABLE_PARITY (5U) |
| #define MMAP_A429_TX_CR_POS_PARITY_TYPE (4U) |
| #define MMAP_A429_TX_CR_POS_PRESCALE (6U) |
| #define MMAP_A429_TX_CR_POS_RUN (7U) |
| #define MMAP_A429_TX_CR_POS_SKIP (3U) |
| #define MMAP_A429_TX_CR_POS_SPEED (1U) |
| #define MMAP_A429_TX_DF_COUNT_BASE (0x031CU) |
| #define MMAP_A429_TX_FIFO_COUNT_BASE (0x02BCU) |
| #define MMAP_A429_TX_FIFO_COUNT_BITMASK (0x1FU) |
| #define MMAP_A429_TX_FIFO_COUNT_ENABLE_BITMASK (0x20U) |
| #define MMAP_A429_TX_FIFO_DISABLE_FLAG (0U) |
| #define MMAP_A429_TX_FIFO_ENABLE_FLAG (0x08U) |
| #define MMAP_A429_TX_FIFO_MESSAGE_BASE (0x02C0U) |
| #define MMAP_A429_TX_FLAG_BASE (0x00A4U) |
| #define MMAP_A429_TX_FLAG_FIFO_ALMOST_FULL_BITMASK (0x02U) |
| #define MMAP_A429_TX_FLAG_FIFO_EMPTY_BITMASK (0x01U) |
| #define MMAP_A429_TX_FLAG_FIFO_FULL_BITMASK (0x04U) |
| #define MMAP_A429_TX_MESSAGE_COUNT_BASE (0x033CU) |
| #define MMAP_A429_TX_RR_BASE (0x02FCU) |
| #define MMAP_A429_TX_SCH_ADDR_GAP (0x04U) |
| #define MMAP_A429_TX_SCH_CH_GAP (0x1000U) |
1.18.0