Memory Maps

Hardware register memory map definitions, base address offsets, and register bitmasks for all modules and drivers. More...

Collaboration diagram for Memory Maps:

Topics
	ARINC 429 Memory Map
	Register offsets, bitmasks, and channel gap definitions for ARINC 429 transceivers (mmapA429.h).
	Analog Input Memory Map
	Register offsets, PGA gain settings, and ADC sequencer maps (mmapAnalogIn.h).
	Core System Memory Map
	System chassis control, reset registers, and core hardware status bitmasks (mmapCore.h).
	NVSRAM Memory Map
	Non-volatile SRAM memory address layout, calibration offsets, and BIT log storage (coreNvsramMap.h).
	Discrete Input Memory Map
	Multi-bank discrete input registers, debounce configurations, and BIT states (mmapDiscreteIn.h).
	Discrete Output Memory Map
	Discrete output control registers, current limit flags, and coil drivers (mmapDiscreteOut.h).
	Power Supply Unit Memory Map
	Power supply telemetry registers, voltage rails, and thermal sensor offsets (mmapPsu.h).
	PWM Actuation Memory Map
	Pulse width modulation frequency, duty cycle, and actuation control registers (mmapPwm.h).
	RVDT Sensor Memory Map
	Demodulator registers, excitation frequency offsets, and angular position mapping (mmapRvdt.h).
	Inter-Driver Shared Memory Map
	Inter-driver shared memory buffer definitions, PCIe aperture offsets, and status blocks (memoryMap.h).

Detailed Description

Hardware register memory map definitions, base address offsets, and register bitmasks for all modules and drivers.

HFCC-01 Hardware Memory Map Architecture Overview

The Low-Level Device Drivers (LLDD) interface directly with hardware peripherals via PCIe Memory-Mapped I/O (MMIO) windows mapped through the FPGA AXI interconnect. Each peripheral defines its base address offsets, control/status registers, bitmasks, and channel gap spacing in dedicated memory map headers:

Subsystem / Peripheral	Base Offset	Header File	Access Mode	Description
ARINC 429 Transceiver	0x5000 / 0x1000	mmapA429.h	R/W	16-channel ARINC 429 controller, FIFOs, and label filters
Analog Input (ADC)	0x3000	mmapAnalogIn.h	R/W	Multichannel ADC sequencer, PGA gain registers, and raw count buffers
Core System Controller	0x0000	mmapCore.h	R/W	Chassis control, board reset, watchdog, and general status
NVSRAM Non-Volatile Memory	0x0000	coreNvsramMap.h	R/W	Flight log storage, PBIT/CBIT health history, and calibration tables
Discrete Input (DIN)	0x2000	mmapDiscreteIn.h	R	Multi-bank discrete digital sensing and input BIT registers
Discrete Output (DOUT)	0x1000	mmapDiscreteOut.h	R/W	High-side/low-side discrete driver banks, wraps, and fault registers
Power Supply Unit (PSU)	0x4000	mmapPsu.h	R/W	Voltage/current telemetry, rail power good monitors, and temperature
Pulse Width Modulation (PWM)	0x1000	mmapPwm.h	R/W	4-channel PWM period, duty cycle, enable, and frequency registers
RVDT Demodulation & Sensor	0x4000	mmapRvdt.h	R/W	Primary/secondary excitation, phase demodulator, and position registers
Inter-Driver Shared Memory	0x0000	memoryMap.h	R/W	Shared memory regions, PCIe BAR translation, and driver IPC