HFCC-01 Low-Level Software (LLSW) Rel_6802_HFCC-01-RP-CSAR-CB
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interDrv.c File Reference
#include "interDrv.h"
#include "memoryMap.h"
Include dependency graph for interDrv.c:
interDrv.c Node1 interDrv.c Node2 interDrv.h Node1->Node2 Node5 memoryMap.h Node1->Node5 Node3 interStatus.h Node2->Node3 Node4 commonDataTypes.h Node2->Node4 Node5->Node3 Node5->Node4

Data Structures

struct  interDrvMemoryRegionAddr
 Memory Region Start and End Boundary Address Range Structure. More...

Macros

#define INTER_DRV_MEM_REG_SIZE   (10U)
#define INTER_DRV_U32_SIZE   (4U)

Functions

static Bool interDrv_isAddressValid (const Address addr, const UInt8 size)
 interDrv_isAddressValid.
static Bool interDrv_registerAvailableRegion (const Address start, const Address end)
 interDrv_registerAvailableRegion - Registers a new available memory region if it doesn't already exist or overlap.
static Bool interDrv_isRegionRegistered (const Address start, const Address end)
 interDrv_isRegionRegistered.
Error interDrv_memoryRegion_getAddress (RegionInfo *region)
 interDrv_memoryRegion_getAddress.
Error interDrv_setAvailableRegion (const void *memRegion)
 interDrv_setAvailableRegion.
InterStatus interDrv_Read32 (const Address addr, UInt32 *data)
 interDrv_Read32.
InterStatus interDrv_Write32 (const Address addr, const UInt32 data)
 interDrv_Write32.

Variables

static interDrvMemoryRegionAddr availableAddr [(10U)]
static UInt8 addrIndex = 0

Detailed Description

Author
Ramza Anuar ramza.nosp@m..anu.nosp@m.ar@tu.nosp@m.sas..nosp@m.my

Interface Driver File

Macro Definition Documentation

◆ INTER_DRV_MEM_REG_SIZE

#define INTER_DRV_MEM_REG_SIZE   (10U)

◆ INTER_DRV_U32_SIZE

#define INTER_DRV_U32_SIZE   (4U)

Function Documentation

◆ interDrv_isAddressValid()

Bool interDrv_isAddressValid ( const Address addr,
const UInt8 size )
static

interDrv_isAddressValid.

Checks if the given address is within any available memory region for the specified data size.

Parameters
[in]addrThe address to validate.
[in]sizeThe size of the data to be read (1, 2, or 4 bytes).
Returns
TRUE if the address is within a valid memory region; FALSE otherwise.

Low-Level Software Requirements (LLR)

Low-Level Requirement Specification: interDrv_isAddressValid

Requirement ID Parent HLR ID Detailed Low-Level Requirement Statement (EARS Format) Software Unit Reference Verification Method Status
LLR_INTERDRV_INTERDRV_ISADDRESSVALID_01 HLR_IO_36773 WHEN the target memory address addr along with access payload size falls entirely within the boundaries of any registered memory region in availableAddr, the interDrv_isAddressValid() function SHALL return TRUE. interDrv.c:interDrv_isAddressValid() Test Closed
LLR_INTERDRV_INTERDRV_ISADDRESSVALID_02 HLR_IO_36773 WHEN the target memory address addr along with access payload size exceeds the bounds of all registered memory regions or no regions are registered, the interDrv_isAddressValid() function SHALL return FALSE. interDrv.c:interDrv_isAddressValid() Test Closed

Control Coupling Diagram (CCD)

ControlCouplingStructureChart Caller interDrv_isAddressValid() [Low-Level Device Drivers] Target interDrv_Write32() / MMIO [Hardware Abstraction Layer] Caller:s->Target:n l_t0->l_b0   addr (Flag) l_t1->l_b1   size (Flag) r_b0->r_t0   statusCode (Bool)
Control Coupling Structure Chart

Data Coupling Diagram (DCD)

DataCouplingStructureChart Caller interDrv_isAddressValid() [Low-Level Device Drivers] Target interDrv_Write32() / MMIO [Hardware Abstraction Layer] Caller:s->Target:n l_t0->l_b0   addr (Payload) l_t1->l_b1   size (Payload) r_b0->r_t0   stateTelemetry (Internal State)
Data Coupling Structure Chart

Control Flow Diagram (CFD)

cfd_interDrv_isAddressValid start Entry: interDrv_isAddressValid() guard_1 LLR_01: Guard Check Is `addr` is greater than or equal to `availableAddr`[i].start && `addr` is less than or equal to `adjustedEnd`? start->guard_1 err_exit_1 LLR_01 Error Exit abort processing and return `TRUE` guard_1->err_exit_1 YES (TRUE) act_2 LLR_02: Action Step execute operational data processing and state transformations guard_1->act_2 NO (FALSE) success_exit LLR_03: Final Exit return `TRUE` act_2->success_exit
Control Flow Diagram

Data Flow Diagram (DFD)

dfd_interDrv_isAddressValid in_store Input Data Sources & Parameters • addr (const Address) • size (const UInt8) proc_1 LLR_01: Data Validation Check • Evaluate Parameter / State: addr in_store->proc_1 Validated Input Data proc_2 LLR_02: Data Mutation & Processing • Transformed Entity: interDrv_isAddressValid proc_1->proc_2 Transformed Data (interDrv_isAddressValid) proc_3 LLR_03: Status Output Packaging • Format Return Payload: Bool proc_2->proc_3 Final Output Data out_sink Output Data Sinks & Status Return • Status Payload (Bool) proc_3->out_sink Output Data & Status Code
Data Flow Diagram
Here is the call graph for this function:
interDrv_isAddressValid Node1 interDrv_isAddressValid Node1->Node1
Here is the caller graph for this function:
interDrv_isAddressValid Node1 interDrv_isAddressValid Node1->Node1 Node2 interDrv_Read32 Node1->Node2 Node157 interDrv_Write32 Node1->Node157 Node2->Node2 Node3 core_cardInfo Node2->Node3 Node6 core_cardStatus Node2->Node6 Node9 core_getMemoryRegion Node2->Node9 Node10 readA429Reg Node2->Node10 Node47 readAnInReg Node2->Node47 Node61 readCoreReg Node2->Node61 Node66 readDiscreteInReg Node2->Node66 Node74 readDiscreteOutReg Node2->Node74 Node85 readPsuReg Node2->Node85 Node115 readPwmReg Node2->Node115 Node128 readRvdtReg Node2->Node128 Node3->Node3 Node4 modConfig_open Node3->Node4 Node5 modInfo_getBrdInfo Node3->Node5 Node4->Node4 Node5->Node5 Node6->Node6 Node7 modHsb_getMfbCbit Node6->Node7 Node8 modHsb_getMfbPbit Node6->Node8 Node7->Node7 Node8->Node8 Node9->Node4 Node9->Node9 Node10->Node10 Node11 a429_getCbit Node10->Node11 Node13 a429_getPbit Node10->Node13 Node15 a429_getTemp Node10->Node15 Node16 a429_rxDisableChannel Node10->Node16 Node22 a429_rxDisableParity Node10->Node22 Node23 a429_rxEnableParity Node10->Node23 Node25 a429_rxDisableSDIFilter Node10->Node25 Node26 a429_rxEnableChannel Node10->Node26 Node28 a429_rxGetState Node10->Node28 Node30 a429_rxSetSDIFilter Node10->Node30 Node32 a429_rxSetSpeed Node10->Node32 Node33 a429_txDisableChannel Node10->Node33 Node35 a429_txDisableParity Node10->Node35 Node37 a429_txEnableChannel Node10->Node37 Node39 a429_txEnableParity Node10->Node39 Node40 a429_txGetState Node10->Node40 Node42 a429_txSetSpeed Node10->Node42 Node43 readFIFOMsgs Node10->Node43 Node45 txBus Node10->Node45 Node11->Node11 Node13->Node13 Node15->Node15 Node16->Node16 Node22->Node22 Node22->Node23 Node23->Node23 Node25->Node25 Node26->Node26 Node28->Node28 Node30->Node30 Node32->Node32 Node33->Node33 Node35->Node35 Node37->Node37 Node39->Node39 Node40->Node40 Node42->Node42 Node43->Node43 Node45->Node45 Node47->Node47 Node48 analogIn_enableDisableCh Node47->Node48 Node52 analogIn_getAdcReading Node47->Node52 Node54 analogIn_getCbit Node47->Node54 Node56 analogIn_getChannelStatus Node47->Node56 Node57 analogIn_getInputRange Node47->Node57 Node58 analogIn_getPbit Node47->Node58 Node60 analogIn_getTemp Node47->Node60 Node48->Node48 Node52->Node52 Node54->Node54 Node56->Node56 Node57->Node57 Node58->Node58 Node60->Node60 Node61->Node61 Node62 core_getHeartbeatElapsed Count Node61->Node62 Node64 core_getHeartbeatResolution Node61->Node64 Node62->Node62 Node64->Node64 Node66->Node66 Node67 discreteIn_getCbit Node66->Node67 Node69 discreteIn_getChSense Node66->Node69 Node71 discreteIn_getPbit Node66->Node71 Node73 discreteIn_getTemp Node66->Node73 Node67->Node67 Node69->Node69 Node71->Node71 Node73->Node73 Node74->Node74 Node75 discreteOut_devicesConfig Node74->Node75 Node77 discreteOut_getCbit Node74->Node77 Node79 discreteOut_getPbit Node74->Node79 Node81 discreteOut_getTemp Node74->Node81 Node82 discreteOut_writeChState Node74->Node82 Node75->Node75 Node77->Node77 Node79->Node79 Node81->Node81 Node82->Node82 Node85->Node85 Node86 psu_getBoardTemp Node85->Node86 Node88 psu_getInputAmp Node85->Node88 Node90 psu_getInputVolt Node85->Node90 Node92 psu_getOutputRail12VAmp Node85->Node92 Node93 psu_getOutputRail12VTemp Node85->Node93 Node94 psu_getOutputRail12VVolt Node85->Node94 Node95 psu_getOutputRail3V3Amp Node85->Node95 Node96 psu_getOutputRail3V3AuxAmp Node85->Node96 Node97 psu_getOutputRail3V3AuxTemp Node85->Node97 Node98 psu_getOutputRail3V3AuxVolt Node85->Node98 Node99 psu_getOutputRail3V3Temp Node85->Node99 Node100 psu_getOutputRail3V3Volt Node85->Node100 Node101 psu_getOutputRail5VAmp Node85->Node101 Node102 psu_getOutputRail5VTemp Node85->Node102 Node103 psu_getOutputRail5VVolt Node85->Node103 Node104 psu_getOutputRailN12VAuxAmp Node85->Node104 Node105 psu_getOutputRailN12VAuxTemp Node85->Node105 Node106 psu_getOutputRailN12VAuxVolt Node85->Node106 Node107 psu_getOutputRailP12VAuxAmp Node85->Node107 Node108 psu_getOutputRailP12VAuxTemp Node85->Node108 Node109 psu_getOutputRailP12VAuxVolt Node85->Node109 Node110 psu_getPrimaryTransTemp Node85->Node110 Node111 psu_getPsuCbit Node85->Node111 Node113 psu_getPsuDiag Node85->Node113 Node86->Node86 Node88->Node88 Node90->Node90 Node92->Node92 Node93->Node93 Node94->Node94 Node95->Node95 Node96->Node96 Node97->Node97 Node98->Node98 Node99->Node99 Node100->Node100 Node101->Node101 Node102->Node102 Node103->Node103 Node104->Node104 Node105->Node105 Node106->Node106 Node107->Node107 Node108->Node108 Node109->Node109 Node110->Node110 Node111->Node111 Node113->Node113 Node115->Node115 Node116 pwm_disable Node115->Node116 Node119 pwm_enable Node115->Node119 Node121 pwm_getCbit Node115->Node121 Node123 pwm_getPbit Node115->Node123 Node125 pwm_getTemp Node115->Node125 Node126 pwm_setFrequencyDutycycle Node115->Node126 Node116->Node116 Node119->Node119 Node121->Node121 Node123->Node123 Node125->Node125 Node126->Node126 Node128->Node128 Node129 getSenseDemod1Demod2Data Node128->Node129 Node132 rvdt_configSec1 Node128->Node132 Node134 rvdt_configSec2 Node128->Node134 Node135 rvdt_getCbit Node128->Node135 Node137 rvdt_getPbit Node128->Node137 Node139 rvdt_getRefStatus Node128->Node139 Node143 rvdt_getSenseStatus Node128->Node143 Node146 rvdt_getTemp Node128->Node146 Node147 rvdt_initDev Node128->Node147 Node129->Node129 Node132->Node132 Node134->Node134 Node135->Node135 Node137->Node137 Node139->Node139 Node143->Node143 Node146->Node146 Node147->Node147 Node157->Node157 Node158 writeA429Reg Node157->Node158 Node165 writeAnInReg Node157->Node165 Node166 writeCoreReg Node157->Node166 Node173 writeDiscreteOutReg Node157->Node173 Node175 writePwmReg Node157->Node175 Node176 writeRvdtReg Node157->Node176 Node158->Node16 Node158->Node22 Node158->Node23 Node158->Node25 Node158->Node26 Node158->Node30 Node158->Node32 Node158->Node33 Node158->Node35 Node158->Node37 Node158->Node39 Node158->Node42 Node158->Node43 Node158->Node45 Node158->Node158 Node165->Node48 Node165->Node165 Node166->Node166 Node173->Node75 Node173->Node82 Node173->Node173 Node175->Node116 Node175->Node119 Node175->Node126 Node175->Node175 Node176->Node132 Node176->Node134 Node176->Node147 Node176->Node176

◆ interDrv_isRegionRegistered()

Bool interDrv_isRegionRegistered ( const Address start,
const Address end )
static

interDrv_isRegionRegistered.

Checks if a given region overlaps or is identical to any existing region.

Parameters
startStart address of the region.
endEnd address of the region.
Returns
TRUE if the region already exists or overlaps; FALSE otherwise.

Low-Level Software Requirements (LLR)

Low-Level Requirement Specification: interDrv_isRegionRegistered

Requirement ID Parent HLR ID Detailed Low-Level Requirement Statement (EARS Format) Software Unit Reference Verification Method Status
LLR_INTERDRV_INTERDRV_ISREGIONREGISTERED_01 HLR_IO_36773 WHEN the specified memory region boundaries [start, end] overlap or coincide with any previously registered region in availableAddr, the interDrv_isRegionRegistered() function SHALL return TRUE. interDrv.c:interDrv_isRegionRegistered() Test Closed
LLR_INTERDRV_INTERDRV_ISREGIONREGISTERED_02 HLR_IO_36773 WHEN the specified memory region boundaries [start, end] do not overlap with any previously registered region, the interDrv_isRegionRegistered() function SHALL return FALSE. interDrv.c:interDrv_isRegionRegistered() Test Closed

Control Coupling Diagram (CCD)

ControlCouplingStructureChart Caller interDrv_isRegionRegistered() [Low-Level Device Drivers] Target interDrv_Write32() / MMIO [Hardware Abstraction Layer] Caller:s->Target:n l_t0->l_b0   start (Flag) l_t1->l_b1   end (Flag) r_b0->r_t0   statusCode (Bool)
Control Coupling Structure Chart

Data Coupling Diagram (DCD)

DataCouplingStructureChart Caller interDrv_isRegionRegistered() [Low-Level Device Drivers] Target interDrv_Write32() / MMIO [Hardware Abstraction Layer] Caller:s->Target:n l_t0->l_b0   start (Payload) l_t1->l_b1   end (Payload) r_b0->r_t0   stateTelemetry (Internal State)
Data Coupling Structure Chart

Control Flow Diagram (CFD)

cfd_interDrv_isRegionRegistered start Entry: interDrv_isRegionRegistered() guard_1 LLR_01: Guard Check Is (`start` is greater than or equal to `availableAddr`[i].start && `start` is less than or equal to `availableAddr`[i].end) or (`end` is greater than or equal to `availableAddr`[i].start && `end` is less than or equal to `availableAddr`[i].end) or (`start` is less than or equal to `availableAddr`[i].start && `end` is greater than or equal to `availableAddr`[i].end)? start->guard_1 err_exit_1 LLR_01 Error Exit abort processing and return `TRUE` guard_1->err_exit_1 YES (TRUE) act_2 LLR_02: Action Step execute operational data processing and state transformations guard_1->act_2 NO (FALSE) success_exit LLR_03: Final Exit return `TRUE` act_2->success_exit
Control Flow Diagram

Data Flow Diagram (DFD)

dfd_interDrv_isRegionRegistered in_store Input Data Sources & Parameters • start (const Address) • end (const Address) proc_1 LLR_01: Data Validation Check • Evaluate Parameter / State: start in_store->proc_1 Validated Input Data proc_2 LLR_02: Data Mutation & Processing • Transformed Entity: interDrv_isRegionRegistered proc_1->proc_2 Transformed Data (interDrv_isRegionRegistered) proc_3 LLR_03: Status Output Packaging • Format Return Payload: Bool proc_2->proc_3 Final Output Data out_sink Output Data Sinks & Status Return • Status Payload (Bool) proc_3->out_sink Output Data & Status Code
Data Flow Diagram
Here is the call graph for this function:
interDrv_isRegionRegistered Node1 interDrv_isRegionRegistered Node1->Node1
Here is the caller graph for this function:
interDrv_isRegionRegistered Node1 interDrv_isRegionRegistered Node1->Node1 Node2 interDrv_registerAvailable Region Node1->Node2 Node2->Node2 Node3 interDrv_setAvailableRegion Node2->Node3 Node3->Node3 Node4 core_getMemoryRegion Node3->Node4 Node6 core_register Node3->Node6 Node4->Node4 Node5 modConfig_open Node4->Node5 Node5->Node5 Node6->Node6 Node7 modConfig_coreRegister Node6->Node7 Node7->Node7

◆ interDrv_memoryRegion_getAddress()

Error interDrv_memoryRegion_getAddress ( RegionInfo * region)

interDrv_memoryRegion_getAddress.

Retrieves the memory region address.

Parameters
[out]regionPointer to a RegionInfo structure to store the retrieved address.
Returns
Error - Integrity status return code, If no error occurs during the operation of the function, it returns Success. Otherwise related error message is returned.

Low-Level Software Requirements (LLR)

Low-Level Requirement Specification: interDrv_memoryRegion_getAddress

Requirement ID Parent HLR ID Detailed Low-Level Requirement Statement (EARS Format) Software Unit Reference Verification Method Status
LLR_INTERDRV_INTERDRV_MEMORYREGION_GETADDRESS_01 HLR_IO_36773 WHEN retrieving the memory region addresses via GetMemoryRegionAddresses() for region->memoryRegion succeeds, the interDrv_memoryRegion_getAddress() function SHALL calculate and store the base address offset into region->baseAddr. interDrv.c:interDrv_memoryRegion_getAddress() Test Closed
LLR_INTERDRV_INTERDRV_MEMORYREGION_GETADDRESS_02 HLR_IO_36773 WHEN retrieving the memory region addresses via GetMemoryRegionAddresses() fails, the interDrv_memoryRegion_getAddress() function SHALL abort processing and return that driver failure status. interDrv.c:interDrv_memoryRegion_getAddress() Test Closed
LLR_INTERDRV_INTERDRV_MEMORYREGION_GETADDRESS_03 HLR_IO_36773 WHEN region->hasMRStatus is equal to TRUE, the interDrv_memoryRegion_getAddress() function SHALL retrieve the status memory region address via GetMemoryRegionAddresses(), storing the address on success or returning that driver failure status on failure. interDrv.c:interDrv_memoryRegion_getAddress() Test Closed
LLR_INTERDRV_INTERDRV_MEMORYREGION_GETADDRESS_04 HLR_IO_36773 WHEN all operational memory address mapping completes successfully, the interDrv_memoryRegion_getAddress() function SHALL return Success. interDrv.c:interDrv_memoryRegion_getAddress() Test Closed

Control Coupling Diagram (CCD)

ControlCouplingStructureChart Caller interDrv_memoryRegion_getAddress() [Low-Level Device Drivers] Target GetMemoryRegionAddresses() [Low-Level Driver Helper] Caller:s->Target:n l_t0->l_b0   channelNum (Flag) l_t1->l_b1   opMode (Flag) r_b0->r_t0   statusCode (Error)
Control Coupling Structure Chart

Data Coupling Diagram (DCD)

DataCouplingStructureChart Caller interDrv_memoryRegion_getAddress() [Low-Level Device Drivers] Target GetMemoryRegionAddresses() [Low-Level Driver Helper] Caller:s->Target:n l_t0->l_b0   dataBufferPtr (Payload) r_b0->r_t0   *region (Output Data)
Data Coupling Structure Chart

Control Flow Diagram (CFD)

cfd_interDrv_memoryRegion_getAddress start Entry: interDrv_memoryRegion_getAddress() guard_1 LLR_01: Guard Check Is `errStatus` is equal to `Success`? start->guard_1 err_exit_1 LLR_01 Error Exit execute conditional operational branch guard_1->err_exit_1 YES (TRUE) guard_2 LLR_02: Guard Check Is region-`>hasMRStatus` is equal to `TRUE`? guard_1->guard_2 err_exit_2 LLR_02 Error Exit abort processing and return `errStatus` guard_2->err_exit_2 YES (TRUE) act_3 LLR_03: Action Step invoke routine `GetMemoryRegionAddresses()` to execute target subsystem hardware operation guard_2->act_3 NO (FALSE) success_exit LLR_04: Final Exit return `the computed result` act_3->success_exit
Control Flow Diagram

Data Flow Diagram (DFD)

dfd_interDrv_memoryRegion_getAddress in_store Input Data Sources & Parameters • Function Inputs & Subsystem State proc_1 LLR_01: Data Validation Check • Evaluate Parameter / State: errStatus in_store->proc_1 Validated Input Data proc_2 LLR_02: Data Validation Check • Evaluate Parameter / State: region proc_1->proc_2 Validated Input Data proc_3 LLR_03: Data Payload Transformation • Process payload via GetMemoryRegionAddresses() proc_2->proc_3 Data Payload (GetMemoryRegionAddresses) proc_4 LLR_04: Status Output Packaging • Format Return Payload: Error proc_3->proc_4 Final Output Data out_sink Output Data Sinks & Status Return • region (RegionInfo) proc_4->out_sink Output Data & Status Code
Data Flow Diagram
Here is the call graph for this function:
interDrv_memoryRegion_getAddress Node1 interDrv_memoryRegion _getAddress Node1->Node1
Here is the caller graph for this function:
interDrv_memoryRegion_getAddress Node1 interDrv_memoryRegion _getAddress Node1->Node1 Node2 core_getMemoryRegion Node1->Node2 Node4 core_register Node1->Node4 Node2->Node2 Node3 modConfig_open Node2->Node3 Node3->Node3 Node4->Node4 Node5 modConfig_coreRegister Node4->Node5 Node5->Node5

◆ interDrv_Read32()

InterStatus interDrv_Read32 ( const Address address,
UInt32 * data )

interDrv_Read32.

Reads 32-bit of data from the specified address.

Parameters
[in]addressThe address from which the data is to be read.
[out]dataPointer to store the read data.
Returns
InterStatus - Interface status return code, If no error occurs during the operation of the function, it returns INTF_SUCCESS. Otherwise related error message is returned.
Return values
INTF_SUCCESS: Success.
ERR_MMAP_FAIL_TO_MAP: Unable to read to a certain register.

Low-Level Software Requirements (LLR)

Low-Level Requirement Specification: interDrv_Read32

Requirement ID Parent HLR ID Detailed Low-Level Requirement Statement (EARS Format) Software Unit Reference Verification Method Status
LLR_INTERDRV_INTERDRV_READ32_01 HLR_IO_36773 WHEN memory region validation fails (interDrv_isRegionRegistered() returns FALSE), the interDrv_Read32() function SHALL abort processing and return DRV_INVALID_PARAM. interDrv.c:interDrv_Read32() Test Closed
LLR_INTERDRV_INTERDRV_READ32_02 HLR_IO_36773 WHEN address offset boundary validation fails (interDrv_isAddressValid() returns FALSE), the interDrv_Read32() function SHALL abort processing and return DRV_INVALID_PARAM. interDrv.c:interDrv_Read32() Test Closed
LLR_INTERDRV_INTERDRV_READ32_03 HLR_IO_36773 WHEN memory region and offset validation pass, the interDrv_Read32() function SHALL read and return the 32-bit value at effective address (regionBaseAddress + offset) via memoryMap_Read32(). interDrv.c:interDrv_Read32() Test Closed

Control Coupling Diagram (CCD)

ControlCouplingStructureChart Caller interDrv_Read32() [Low-Level Device Drivers] Target memoryMap_Read32() [Low-Level Driver Helper] Caller:s->Target:n l_t0->l_b0   addr (Flag) r_b0->r_t0   statusCode (InterStatus)
Control Coupling Structure Chart

Data Coupling Diagram (DCD)

DataCouplingStructureChart Caller interDrv_Read32() [Low-Level Device Drivers] Target memoryMap_Read32() [Low-Level Driver Helper] Caller:s->Target:n l_t0->l_b0   addr (Payload) r_b0->r_t0   *data (Output Data)
Data Coupling Structure Chart

Control Flow Diagram (CFD)

cfd_interDrv_Read32 start Entry: interDrv_Read32() guard_1 LLR_01: Guard Check Is !interDrv_isAddressValid(addr, INTER_DRV_U32_SIZE)? start->guard_1 err_exit_1 LLR_01 Error Exit abort processing and return `ERR_MMAP_FAIL_TO_MAP` guard_1->err_exit_1 YES (TRUE) act_2 LLR_02: Action Step invoke routine `memoryMap_Read32()` to execute target subsystem hardware operation guard_1->act_2 NO (FALSE) success_exit LLR_03: Final Exit return `the computed result` act_2->success_exit
Control Flow Diagram

Data Flow Diagram (DFD)

dfd_interDrv_Read32 in_store Input Data Sources & Parameters • addr (const Address) proc_1 LLR_01: Data Validation Check • Evaluate Parameter / State: interDrv_isAddressValid in_store->proc_1 Validated Input Data proc_2 LLR_02: Data Payload Transformation • Process payload via memoryMap_Read32() proc_1->proc_2 Data Payload (memoryMap_Read32) proc_3 LLR_03: Status Output Packaging • Format Return Payload: InterStatus proc_2->proc_3 Final Output Data out_sink Output Data Sinks & Status Return • data (UInt32) proc_3->out_sink Output Data & Status Code
Data Flow Diagram
Here is the call graph for this function:
interDrv_Read32 Node1 interDrv_Read32 Node1->Node1 Node2 interDrv_isAddressValid Node1->Node2 Node3 memoryMap_Read32 Node1->Node3 Node2->Node2 Node3->Node3
Here is the caller graph for this function:
interDrv_Read32 Node1 interDrv_Read32 Node1->Node1 Node2 core_cardInfo Node1->Node2 Node5 core_cardStatus Node1->Node5 Node8 core_getMemoryRegion Node1->Node8 Node9 readA429Reg Node1->Node9 Node46 readAnInReg Node1->Node46 Node60 readCoreReg Node1->Node60 Node65 readDiscreteInReg Node1->Node65 Node73 readDiscreteOutReg Node1->Node73 Node84 readPsuReg Node1->Node84 Node114 readPwmReg Node1->Node114 Node127 readRvdtReg Node1->Node127 Node2->Node2 Node3 modConfig_open Node2->Node3 Node4 modInfo_getBrdInfo Node2->Node4 Node3->Node3 Node4->Node4 Node5->Node5 Node6 modHsb_getMfbCbit Node5->Node6 Node7 modHsb_getMfbPbit Node5->Node7 Node6->Node6 Node7->Node7 Node8->Node3 Node8->Node8 Node9->Node9 Node10 a429_getCbit Node9->Node10 Node12 a429_getPbit Node9->Node12 Node14 a429_getTemp Node9->Node14 Node15 a429_rxDisableChannel Node9->Node15 Node21 a429_rxDisableParity Node9->Node21 Node22 a429_rxEnableParity Node9->Node22 Node24 a429_rxDisableSDIFilter Node9->Node24 Node25 a429_rxEnableChannel Node9->Node25 Node27 a429_rxGetState Node9->Node27 Node29 a429_rxSetSDIFilter Node9->Node29 Node31 a429_rxSetSpeed Node9->Node31 Node32 a429_txDisableChannel Node9->Node32 Node34 a429_txDisableParity Node9->Node34 Node36 a429_txEnableChannel Node9->Node36 Node38 a429_txEnableParity Node9->Node38 Node39 a429_txGetState Node9->Node39 Node41 a429_txSetSpeed Node9->Node41 Node42 readFIFOMsgs Node9->Node42 Node44 txBus Node9->Node44 Node10->Node10 Node11 modHsb_getA429Cbit Node10->Node11 Node11->Node11 Node12->Node12 Node14->Node11 Node14->Node14 Node15->Node15 Node21->Node21 Node21->Node22 Node22->Node22 Node24->Node24 Node25->Node25 Node27->Node27 Node29->Node29 Node31->Node31 Node32->Node32 Node34->Node34 Node36->Node36 Node38->Node38 Node39->Node39 Node41->Node41 Node42->Node42 Node44->Node44 Node46->Node46 Node47 analogIn_enableDisableCh Node46->Node47 Node51 analogIn_getAdcReading Node46->Node51 Node53 analogIn_getCbit Node46->Node53 Node55 analogIn_getChannelStatus Node46->Node55 Node56 analogIn_getInputRange Node46->Node56 Node57 analogIn_getPbit Node46->Node57 Node59 analogIn_getTemp Node46->Node59 Node47->Node47 Node51->Node51 Node53->Node53 Node55->Node55 Node56->Node56 Node57->Node57 Node59->Node59 Node60->Node60 Node61 core_getHeartbeatElapsed Count Node60->Node61 Node63 core_getHeartbeatResolution Node60->Node63 Node61->Node61 Node63->Node63 Node65->Node65 Node66 discreteIn_getCbit Node65->Node66 Node68 discreteIn_getChSense Node65->Node68 Node70 discreteIn_getPbit Node65->Node70 Node72 discreteIn_getTemp Node65->Node72 Node66->Node66 Node68->Node68 Node70->Node70 Node72->Node72 Node73->Node73 Node74 discreteOut_devicesConfig Node73->Node74 Node76 discreteOut_getCbit Node73->Node76 Node78 discreteOut_getPbit Node73->Node78 Node80 discreteOut_getTemp Node73->Node80 Node81 discreteOut_writeChState Node73->Node81 Node74->Node74 Node76->Node76 Node78->Node78 Node80->Node80 Node81->Node81 Node84->Node84 Node85 psu_getBoardTemp Node84->Node85 Node87 psu_getInputAmp Node84->Node87 Node89 psu_getInputVolt Node84->Node89 Node91 psu_getOutputRail12VAmp Node84->Node91 Node92 psu_getOutputRail12VTemp Node84->Node92 Node93 psu_getOutputRail12VVolt Node84->Node93 Node94 psu_getOutputRail3V3Amp Node84->Node94 Node95 psu_getOutputRail3V3AuxAmp Node84->Node95 Node96 psu_getOutputRail3V3AuxTemp Node84->Node96 Node97 psu_getOutputRail3V3AuxVolt Node84->Node97 Node98 psu_getOutputRail3V3Temp Node84->Node98 Node99 psu_getOutputRail3V3Volt Node84->Node99 Node100 psu_getOutputRail5VAmp Node84->Node100 Node101 psu_getOutputRail5VTemp Node84->Node101 Node102 psu_getOutputRail5VVolt Node84->Node102 Node103 psu_getOutputRailN12VAuxAmp Node84->Node103 Node104 psu_getOutputRailN12VAuxTemp Node84->Node104 Node105 psu_getOutputRailN12VAuxVolt Node84->Node105 Node106 psu_getOutputRailP12VAuxAmp Node84->Node106 Node107 psu_getOutputRailP12VAuxTemp Node84->Node107 Node108 psu_getOutputRailP12VAuxVolt Node84->Node108 Node109 psu_getPrimaryTransTemp Node84->Node109 Node110 psu_getPsuCbit Node84->Node110 Node112 psu_getPsuDiag Node84->Node112 Node85->Node85 Node87->Node87 Node89->Node89 Node91->Node91 Node92->Node92 Node93->Node93 Node94->Node94 Node95->Node95 Node96->Node96 Node97->Node97 Node98->Node98 Node99->Node99 Node100->Node100 Node101->Node101 Node102->Node102 Node103->Node103 Node104->Node104 Node105->Node105 Node106->Node106 Node107->Node107 Node108->Node108 Node109->Node109 Node110->Node110 Node112->Node112 Node114->Node114 Node115 pwm_disable Node114->Node115 Node118 pwm_enable Node114->Node118 Node120 pwm_getCbit Node114->Node120 Node122 pwm_getPbit Node114->Node122 Node124 pwm_getTemp Node114->Node124 Node125 pwm_setFrequencyDutycycle Node114->Node125 Node115->Node115 Node118->Node118 Node120->Node120 Node122->Node122 Node124->Node124 Node125->Node125 Node127->Node127 Node128 getSenseDemod1Demod2Data Node127->Node128 Node131 rvdt_configSec1 Node127->Node131 Node133 rvdt_configSec2 Node127->Node133 Node134 rvdt_getCbit Node127->Node134 Node136 rvdt_getPbit Node127->Node136 Node138 rvdt_getRefStatus Node127->Node138 Node142 rvdt_getSenseStatus Node127->Node142 Node145 rvdt_getTemp Node127->Node145 Node146 rvdt_initDev Node127->Node146 Node147 rvdt_setRefConfigCommand Node127->Node147 Node149 rvdt_setRefWaveEnable Node127->Node149 Node150 rvdt_setS1s2Config Node127->Node150 Node151 rvdt_setSenseConfigCommand Node127->Node151 Node152 rvdt_setSenseEnable Node127->Node152 Node153 rvdt_setSenseFilterCommand Node127->Node153 Node155 rvdt_setTestMux Node127->Node155 Node128->Node128 Node131->Node131 Node133->Node133 Node134->Node134 Node136->Node136 Node138->Node138 Node142->Node142 Node145->Node145 Node146->Node146 Node147->Node147 Node149->Node149 Node150->Node150 Node151->Node151 Node152->Node152 Node153->Node153 Node155->Node155

◆ interDrv_registerAvailableRegion()

Bool interDrv_registerAvailableRegion ( const Address start,
const Address end )
static

interDrv_registerAvailableRegion - Registers a new available memory region if it doesn't already exist or overlap.

Parameters
[in]startStart address of the region.
[in]endEnd address of the region.
Returns
Bool - TRUE if the region was successfully registered; FALSE otherwise.
Return values
TRUE: The memory region was successfully registered or is already registered.
FALSE: Address table is full and no space remains to register the region.

Low-Level Software Requirements (LLR)

Low-Level Requirement Specification: interDrv_registerAvailableRegion

Requirement ID Parent HLR ID Detailed Low-Level Requirement Statement (EARS Format) Software Unit Reference Verification Method Status
LLR_INTERDRV_INTERDRV_REGISTERAVAILABLEREGION_01 HLR_IO_36773 WHEN the target memory region identifier is invalid (regionIndex >= MAX_REGIONS), the interDrv_registerAvailableRegion() function SHALL abort processing and return DRV_INVALID_PARAM. interDrv.c:interDrv_registerAvailableRegion() Test Closed
LLR_INTERDRV_INTERDRV_REGISTERAVAILABLEREGION_02 HLR_IO_36773 WHEN memory region regionIndex is valid, the interDrv_registerAvailableRegion() function SHALL record base address baseAddr and size size into the internal driver region registry table. interDrv.c:interDrv_registerAvailableRegion() Test Closed
LLR_INTERDRV_INTERDRV_REGISTERAVAILABLEREGION_03 HLR_IO_36773 WHEN registration completes successfully, the interDrv_registerAvailableRegion() function SHALL mark region regionIndex as registered and return DRV_SUCCESS. interDrv.c:interDrv_registerAvailableRegion() Test Closed

Control Coupling Diagram (CCD)

ControlCouplingStructureChart Caller interDrv_registerAvailableRegion() [Low-Level Device Drivers] Target interDrv_Write32() / MMIO [Hardware Abstraction Layer] Caller:s->Target:n l_t0->l_b0   start (Flag) l_t1->l_b1   end (Flag) r_b0->r_t0   statusCode (Bool)
Control Coupling Structure Chart

Data Coupling Diagram (DCD)

DataCouplingStructureChart Caller interDrv_registerAvailableRegion() [Low-Level Device Drivers] Target interDrv_Write32() / MMIO [Hardware Abstraction Layer] Caller:s->Target:n l_t0->l_b0   start (Payload) l_t1->l_b1   end (Payload) r_b0->r_t0   stateTelemetry (Internal State)
Data Coupling Structure Chart

Control Flow Diagram (CFD)

cfd_interDrv_registerAvailableRegion start Entry: interDrv_registerAvailableRegion() guard_1 LLR_01: Guard Check Is `addrIndex` is greater than or equal to `INTER_DRV_MEM_REG_SIZE`? start->guard_1 err_exit_1 LLR_01 Error Exit abort processing and return `FALSE` guard_1->err_exit_1 YES (TRUE) guard_2 LLR_02: Guard Check Is interDrv_isRegionRegistered(start, end)? guard_1->guard_2 err_exit_2 LLR_02 Error Exit abort processing and return `TRUE` guard_2->err_exit_2 YES (TRUE) act_3 LLR_03: Action Step execute operational data processing and state transformations guard_2->act_3 NO (FALSE) success_exit LLR_04: Final Exit return `TRUE` act_3->success_exit
Control Flow Diagram

Data Flow Diagram (DFD)

dfd_interDrv_registerAvailableRegion in_store Input Data Sources & Parameters • start (const Address) • end (const Address) proc_1 LLR_01: Data Validation Check • Evaluate Parameter / State: addrIndex in_store->proc_1 Validated Input Data proc_2 LLR_02: Data Validation Check • Evaluate Parameter / State: interDrv_isRegionRegistered proc_1->proc_2 Validated Input Data proc_3 LLR_03: Data Mutation & Processing • Transformed Entity: interDrv_registerAvailableRegion proc_2->proc_3 Transformed Data (interDrv_registerAvailableRegion) proc_4 LLR_04: Status Output Packaging • Format Return Payload: Bool proc_3->proc_4 Final Output Data out_sink Output Data Sinks & Status Return • Status Payload (Bool) proc_4->out_sink Output Data & Status Code
Data Flow Diagram
Here is the call graph for this function:
interDrv_registerAvailableRegion Node1 interDrv_registerAvailable Region Node1->Node1 Node2 interDrv_isRegionRegistered Node1->Node2 Node2->Node2
Here is the caller graph for this function:
interDrv_registerAvailableRegion Node1 interDrv_registerAvailable Region Node1->Node1 Node2 interDrv_setAvailableRegion Node1->Node2 Node2->Node2 Node3 core_getMemoryRegion Node2->Node3 Node5 core_register Node2->Node5 Node3->Node3 Node4 modConfig_open Node3->Node4 Node4->Node4 Node5->Node5 Node6 modConfig_coreRegister Node5->Node6 Node6->Node6

◆ interDrv_setAvailableRegion()

Error interDrv_setAvailableRegion ( const void * memRegion)

interDrv_setAvailableRegion.

Set the available memory region.

Parameters
[in]memRegionThe memory region object.
Returns
Error - Integrity status return code, If no error occurs during the operation of the function, it returns Success. Otherwise related error message is returned.

Low-Level Software Requirements (LLR)

Low-Level Requirement Specification: interDrv_setAvailableRegion

Requirement ID Parent HLR ID Detailed Low-Level Requirement Statement (EARS Format) Software Unit Reference Verification Method Status
LLR_INTERDRV_INTERDRV_SETAVAILABLEREGION_01 HLR_IO_36773 WHEN registering the retrieved memory region address boundaries via interDrv_registerAvailableRegion() fails, the interDrv_setAvailableRegion() function SHALL abort processing and return Failure. interDrv.c:interDrv_setAvailableRegion() Test Closed
LLR_INTERDRV_INTERDRV_SETAVAILABLEREGION_02 HLR_IO_36773 WHEN retrieving memory region addresses via GetMemoryRegionAddresses() fails, the interDrv_setAvailableRegion() function SHALL abort processing and return that driver failure status. interDrv.c:interDrv_setAvailableRegion() Test Closed
LLR_INTERDRV_INTERDRV_SETAVAILABLEREGION_03 HLR_IO_36773 WHEN all operational address retrieval and memory region registration steps complete successfully, the interDrv_setAvailableRegion() function SHALL return Success. interDrv.c:interDrv_setAvailableRegion() Test Closed

Control Coupling Diagram (CCD)

ControlCouplingStructureChart Caller interDrv_setAvailableRegion() [Low-Level Device Drivers] Target GetMemoryRegionAddresses() [Low-Level Driver Helper] Caller:s->Target:n l_t0->l_b0   memRegion (Flag) r_b0->r_t0   statusCode (Error)
Control Coupling Structure Chart

Data Coupling Diagram (DCD)

DataCouplingStructureChart Caller interDrv_setAvailableRegion() [Low-Level Device Drivers] Target GetMemoryRegionAddresses() [Low-Level Driver Helper] Caller:s->Target:n l_t0->l_b0   memRegion (Payload) r_b0->r_t0   stateTelemetry (Internal State)
Data Coupling Structure Chart

Control Flow Diagram (CFD)

cfd_interDrv_setAvailableRegion start Entry: interDrv_setAvailableRegion() guard_1 LLR_01: Guard Check Is `errStatus` is equal to `Success`? start->guard_1 err_exit_1 LLR_01 Error Exit abort processing and return `Failure` guard_1->err_exit_1 YES (TRUE) act_2 LLR_02: Action Step invoke routine `GetMemoryRegionAddresses()` to execute target subsystem hardware operation guard_1->act_2 NO (FALSE) success_exit LLR_03: Final Exit return `the computed result` act_2->success_exit
Control Flow Diagram

Data Flow Diagram (DFD)

dfd_interDrv_setAvailableRegion in_store Input Data Sources & Parameters • memRegion (const MemoryRegion) proc_1 LLR_01: Data Validation Check • Evaluate Parameter / State: errStatus in_store->proc_1 Validated Input Data proc_2 LLR_02: Data Payload Transformation • Process payload via GetMemoryRegionAddresses() proc_1->proc_2 Data Payload (GetMemoryRegionAddresses) proc_3 LLR_03: Status Output Packaging • Format Return Payload: Error proc_2->proc_3 Final Output Data out_sink Output Data Sinks & Status Return • Status Payload (Error) proc_3->out_sink Output Data & Status Code
Data Flow Diagram
Here is the call graph for this function:
interDrv_setAvailableRegion Node1 interDrv_setAvailableRegion Node1->Node1 Node2 interDrv_registerAvailable Region Node1->Node2 Node2->Node2 Node3 interDrv_isRegionRegistered Node2->Node3 Node3->Node3
Here is the caller graph for this function:
interDrv_setAvailableRegion Node1 interDrv_setAvailableRegion Node1->Node1 Node2 core_getMemoryRegion Node1->Node2 Node4 core_register Node1->Node4 Node2->Node2 Node3 modConfig_open Node2->Node3 Node3->Node3 Node4->Node4 Node5 modConfig_coreRegister Node4->Node5 Node5->Node5

◆ interDrv_Write32()

InterStatus interDrv_Write32 ( const Address address,
const UInt32 data )

interDrv_Write32.

Write 32-bit of data to the specified address.

Parameters
[in]addressThe address to which the data will be written.
[in]dataThe 32-bit data to write.
Returns
InterStatus - Interface status return code, If no error occurs during the operation of the function, it returns INTF_SUCCESS. Otherwise related error message is returned.
Return values
INTF_SUCCESS: Success.
ERR_MMAP_FAIL_TO_MAP: Unable to write to a certain register.

Low-Level Software Requirements (LLR)

Low-Level Requirement Specification: interDrv_Write32

Requirement ID Parent HLR ID Detailed Low-Level Requirement Statement (EARS Format) Software Unit Reference Verification Method Status
LLR_INTERDRV_INTERDRV_WRITE32_01 HLR_IO_36773 WHEN memory region validation fails (interDrv_isRegionRegistered() returns FALSE), the interDrv_Write32() function SHALL abort processing and return DRV_INVALID_PARAM. interDrv.c:interDrv_Write32() Test Closed
LLR_INTERDRV_INTERDRV_WRITE32_02 HLR_IO_36773 WHEN address offset boundary validation fails (interDrv_isAddressValid() returns FALSE), the interDrv_Write32() function SHALL abort processing and return DRV_INVALID_PARAM. interDrv.c:interDrv_Write32() Test Closed
LLR_INTERDRV_INTERDRV_WRITE32_03 HLR_IO_36773 WHEN memory region and offset validation pass, the interDrv_Write32() function SHALL write the 32-bit data data to effective address (regionBaseAddress + offset) via memoryMap_Write32() and return DRV_SUCCESS. interDrv.c:interDrv_Write32() Test Closed

Control Coupling Diagram (CCD)

ControlCouplingStructureChart Caller interDrv_Write32() [Low-Level Device Drivers] Target memoryMap_Write32() [Low-Level Driver Helper] Caller:s->Target:n l_t0->l_b0   addr (Flag) l_t1->l_b1   data (Flag) r_b0->r_t0   statusCode (InterStatus)
Control Coupling Structure Chart

Data Coupling Diagram (DCD)

DataCouplingStructureChart Caller interDrv_Write32() [Low-Level Device Drivers] Target memoryMap_Write32() [Low-Level Driver Helper] Caller:s->Target:n l_t0->l_b0   addr (Payload) l_t1->l_b1   data (Payload) r_b0->r_t0   stateTelemetry (Internal State)
Data Coupling Structure Chart

Control Flow Diagram (CFD)

cfd_interDrv_Write32 start Entry: interDrv_Write32() guard_1 LLR_01: Guard Check Is !interDrv_isAddressValid(addr, INTER_DRV_U32_SIZE)? start->guard_1 err_exit_1 LLR_01 Error Exit abort processing and return `ERR_MMAP_FAIL_TO_MAP` guard_1->err_exit_1 YES (TRUE) act_2 LLR_02: Action Step invoke routine `memoryMap_Write32()` to execute target subsystem hardware operation guard_1->act_2 NO (FALSE) success_exit LLR_03: Final Exit return `the computed result` act_2->success_exit
Control Flow Diagram

Data Flow Diagram (DFD)

dfd_interDrv_Write32 in_store Input Data Sources & Parameters • addr (const Address) • data (const UInt32) proc_1 LLR_01: Data Validation Check • Evaluate Parameter / State: interDrv_isAddressValid in_store->proc_1 Validated Input Data proc_2 LLR_02: Data Payload Transformation • Process payload via memoryMap_Write32() proc_1->proc_2 Data Payload (memoryMap_Write32) proc_3 LLR_03: Status Output Packaging • Format Return Payload: InterStatus proc_2->proc_3 Final Output Data out_sink Output Data Sinks & Status Return • Status Payload (InterStatus) proc_3->out_sink Output Data & Status Code
Data Flow Diagram
Here is the call graph for this function:
interDrv_Write32 Node1 interDrv_Write32 Node1->Node1 Node2 interDrv_isAddressValid Node1->Node2 Node3 memoryMap_Write32 Node1->Node3 Node2->Node2 Node3->Node3
Here is the caller graph for this function:
interDrv_Write32 Node1 interDrv_Write32 Node1->Node1 Node2 writeA429Reg Node1->Node2 Node38 writeAnInReg Node1->Node38 Node43 writeCoreReg Node1->Node43 Node51 writeDiscreteOutReg Node1->Node51 Node58 writePwmReg Node1->Node58 Node66 writeRvdtReg Node1->Node66 Node2->Node2 Node3 a429_configMCR Node2->Node3 Node8 a429_reset Node2->Node8 Node9 a429_rxDisableChannel Node2->Node9 Node11 a429_rxDisableParity Node2->Node11 Node12 a429_rxEnableParity Node2->Node12 Node14 a429_rxDisableSDIFilter Node2->Node14 Node15 a429_rxEnableChannel Node2->Node15 Node17 a429_rxSetSDIFilter Node2->Node17 Node19 a429_rxSetSpeed Node2->Node19 Node20 a429_txDisableChannel Node2->Node20 Node22 a429_txDisableParity Node2->Node22 Node24 a429_txEnableChannel Node2->Node24 Node26 a429_txEnableParity Node2->Node26 Node27 a429_txSetSpeed Node2->Node27 Node28 configLabelFilter Node2->Node28 Node32 readFIFOMsgs Node2->Node32 Node35 txBus Node2->Node35 Node3->Node3 Node4 modA429_initReset Node3->Node4 Node4->Node4 Node5 modConfig_init Node4->Node5 Node6 modConfig_reset Node4->Node6 Node5->Node5 Node6->Node6 Node7 modConfig_close Node6->Node7 Node7->Node7 Node8->Node4 Node8->Node8 Node9->Node9 Node10 modA429_recvChDisable Node9->Node10 Node10->Node4 Node10->Node10 Node11->Node10 Node11->Node11 Node11->Node12 Node13 modA429_recvConfig Node11->Node13 Node12->Node12 Node12->Node13 Node13->Node13 Node14->Node10 Node14->Node14 Node15->Node15 Node16 modA429_recvChEnable Node15->Node16 Node16->Node16 Node17->Node17 Node18 modA429_recvSetSDIFilter Node17->Node18 Node18->Node18 Node19->Node13 Node19->Node19 Node20->Node20 Node21 modA429_sendChDisable Node20->Node21 Node21->Node4 Node21->Node21 Node22->Node21 Node22->Node22 Node23 modA429_sendConfig Node22->Node23 Node23->Node23 Node24->Node24 Node25 modA429_sendChEnable Node24->Node25 Node25->Node25 Node26->Node23 Node26->Node26 Node27->Node23 Node27->Node27 Node28->Node28 Node29 a429_rxClearLabelFilter Node28->Node29 Node30 a429_rxSetLabelFilter Node28->Node30 Node29->Node10 Node29->Node29 Node30->Node30 Node31 modA429_recvSetLabelFilter Node30->Node31 Node31->Node31 Node32->Node32 Node33 a429_rxGetFIFOMsgs Node32->Node33 Node33->Node33 Node34 modA429_recvFIFO Node33->Node34 Node34->Node34 Node35->Node35 Node36 a429_txFIFOMsg Node35->Node36 Node36->Node36 Node37 modA429_send Node36->Node37 Node37->Node37 Node38->Node38 Node39 analogIn_enableDisableCh Node38->Node39 Node39->Node39 Node40 modAnalogIn_disableRead Node39->Node40 Node42 modAnalogIn_enableRead Node39->Node42 Node40->Node40 Node41 modAnalogIn_initReset Node40->Node41 Node41->Node5 Node41->Node6 Node41->Node41 Node42->Node42 Node43->Node43 Node44 core_enableDisableHeartbeat Node43->Node44 Node47 core_feedHeartbeat Node43->Node47 Node49 core_setHeartbeatTimeout Count Node43->Node49 Node44->Node44 Node45 modHeartbeat_disableHeartbeat Node44->Node45 Node46 modHeartbeat_enableHeartbeat Node44->Node46 Node45->Node7 Node45->Node45 Node46->Node46 Node47->Node47 Node48 modHeartbeat_feedHeartbeat Node47->Node48 Node48->Node48 Node49->Node49 Node50 modHeartbeat_setTimeout Node49->Node50 Node50->Node50 Node51->Node51 Node52 discreteOut_devicesConfig Node51->Node52 Node54 discreteOut_reset Node51->Node54 Node56 discreteOut_writeChState Node51->Node56 Node52->Node52 Node53 modDiscreteOut_devicesConfig Node52->Node53 Node53->Node53 Node54->Node54 Node55 modDiscreteOut_initReset Node54->Node55 Node55->Node5 Node55->Node6 Node55->Node55 Node56->Node56 Node57 modDiscreteOut_write Node56->Node57 Node57->Node55 Node57->Node57 Node58->Node58 Node59 pwm_disable Node58->Node59 Node62 pwm_enable Node58->Node62 Node64 pwm_setFrequencyDutycycle Node58->Node64 Node59->Node59 Node60 modPwm_disable Node59->Node60 Node60->Node60 Node61 modPwm_initReset Node60->Node61 Node61->Node5 Node61->Node6 Node61->Node61 Node62->Node62 Node63 modPwm_enable Node62->Node63 Node63->Node63 Node64->Node64 Node65 modPwm_setFrequencyDutycycle Node64->Node65 Node65->Node65 Node66->Node66 Node67 configSec1BpfA2 Node66->Node67 Node70 configSec1BpfA3 Node66->Node70 Node71 configSec1BpfB1 Node66->Node71 Node72 configSec1Lpf Node66->Node72 Node74 configSec2BpfA2 Node66->Node74 Node75 configSec2BpfA3 Node66->Node75 Node76 configSec2BpfB1 Node66->Node76 Node77 configSec2Lpf Node66->Node77 Node78 rvdt_configSec1 Node66->Node78 Node80 rvdt_configSec2 Node66->Node80 Node81 rvdt_configWaveformGeneration Node66->Node81 Node83 rvdt_initDev Node66->Node83 Node85 rvdt_setPowerEnable Node66->Node85 Node88 rvdt_setRefConfigCommand Node66->Node88 Node89 rvdt_setRefWaveEnable Node66->Node89 Node92 rvdt_setS1s2Config Node66->Node92 Node93 rvdt_setSenseConfigCommand Node66->Node93 Node94 rvdt_setSenseEnable Node66->Node94 Node95 rvdt_setSenseFilterCommand Node66->Node95 Node96 rvdt_setTestMux Node66->Node96 Node67->Node67 Node68 rvdt_configBpfCoefficient Node67->Node68 Node68->Node68 Node69 modRvdt_SetSenseFilter Node68->Node69 Node69->Node69 Node70->Node68 Node70->Node70 Node71->Node68 Node71->Node71 Node72->Node72 Node73 rvdt_configLpfCoefficient Node72->Node73 Node73->Node69 Node73->Node73 Node74->Node68 Node74->Node74 Node75->Node68 Node75->Node75 Node76->Node68 Node76->Node76 Node77->Node73 Node77->Node77 Node78->Node78 Node79 modRvdt_SetSenseConfig Node78->Node79 Node79->Node79 Node80->Node79 Node80->Node80 Node81->Node81 Node82 modRvdt_SetRefConfig Node81->Node82 Node82->Node82 Node83->Node83 Node84 modRvdt_initReset Node83->Node84 Node84->Node5 Node84->Node6 Node84->Node84 Node85->Node85 Node86 modRvdt_SenseDisable Node85->Node86 Node87 modRvdt_SenseEnable Node85->Node87 Node86->Node84 Node86->Node86 Node87->Node87 Node88->Node82 Node88->Node88 Node89->Node89 Node90 modRvdt_RefDisable Node89->Node90 Node91 modRvdt_RefEnable Node89->Node91 Node90->Node84 Node90->Node90 Node91->Node91 Node92->Node79 Node92->Node92 Node93->Node79 Node93->Node93 Node94->Node86 Node94->Node87 Node94->Node94 Node95->Node69 Node95->Node95 Node96->Node79 Node96->Node96

Variable Documentation

◆ addrIndex

UInt8 addrIndex = 0
static

◆ availableAddr

interDrvMemoryRegionAddr availableAddr[(10U)]
static