HFCC-01 Low-Level Software (LLSW) Rel_6802_HFCC-01-RP-CSAR-CB
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memoryMap.c File Reference
#include "memoryMap.h"
Include dependency graph for memoryMap.c:
memoryMap.c Node1 memoryMap.c Node2 memoryMap.h Node1->Node2 Node3 interStatus.h Node2->Node3 Node4 commonDataTypes.h Node2->Node4

Macros

#define endian32(data)

Functions

InterStatus memoryMap_Read32 (const Address address, UInt32 *data)
 memoryMap_Read32.
InterStatus memoryMap_Write32 (const Address address, const UInt32 data)
 memoryMap_Write32.

Detailed Description

Author
Syed Uthman Affan uthma.nosp@m.n.ab.nosp@m.dulha.nosp@m.lim@.nosp@m.tusas.nosp@m..my, Ramza Anuar ramza.nosp@m..anu.nosp@m.ar@tu.nosp@m.sas..nosp@m.my

Memory Map Read and Write Function Header File

Macro Definition Documentation

◆ endian32

#define endian32 ( data)
Value:
((((data) >> 24) & 0x000000FF) | (((data) >> 8) & 0x0000FF00) | (((data) << 8) & 0x00FF0000) | \
(((data) << 24) & 0xFF000000))

Function Documentation

◆ memoryMap_Read32()

InterStatus memoryMap_Read32 ( const Address address,
UInt32 * data )

memoryMap_Read32.

Reads 32-bit of data from the specified address.

Parameters
[in]addressThe address from which the data is to be read.
[out]dataPointer to store the read data.
Returns
InterStatus - Interface status return code, If no error occurs during the operation of the function, it returns INTF_SUCCESS. Otherwise related error message is returned.
Return values
INTF_SUCCESS: Success.
ERR_MMAP_FAIL_TO_MAP: Unable to read to a certain register.

Low-Level Software Requirements (LLR)

Low-Level Requirement Specification: memoryMap_Read32

Requirement ID Parent HLR ID Detailed Low-Level Requirement Statement (EARS Format) Software Unit Reference Verification Method Status
LLR_MEMORYMAP_MEMORYMAP_READ32_01 HLR_IO_36773 WHEN memory address alignment validation fails ((address % 4) != 0), the memoryMap_Read32() function SHALL abort processing and return 0. memoryMap.c:memoryMap_Read32() Test Closed
LLR_MEMORYMAP_MEMORYMAP_READ32_02 HLR_IO_36773 WHEN memory address is 4-byte aligned, the memoryMap_Read32() function SHALL dereference and return the volatile 32-bit unsigned word at memory address address. memoryMap.c:memoryMap_Read32() Test Closed

Control Coupling Diagram (CCD)

ControlCouplingStructureChart Caller memoryMap_Read32() [Low-Level Device Drivers] Target endian32() [Low-Level Driver Helper] Caller:s->Target:n l_t0->l_b0   address (Flag) r_b0->r_t0   statusCode (InterStatus)
Control Coupling Structure Chart

Data Coupling Diagram (DCD)

DataCouplingStructureChart Caller memoryMap_Read32() [Low-Level Device Drivers] Target endian32() [Low-Level Driver Helper] Caller:s->Target:n l_t0->l_b0   address (Payload) r_b0->r_t0   *data (Output Data)
Data Coupling Structure Chart

Control Flow Diagram (CFD)

cfd_memoryMap_Read32 start Entry: memoryMap_Read32() act_1 LLR_01: Action Step invoke routine `endian32()` to execute target subsystem hardware operation start->act_1 success_exit LLR_02: Final Exit return `the computed result` act_1->success_exit
Control Flow Diagram

Data Flow Diagram (DFD)

dfd_memoryMap_Read32 in_store Input Data Sources & Parameters • address (const Address) proc_1 LLR_01: Data Payload Transformation • Process payload via endian32() in_store->proc_1 Data Payload (endian32) proc_2 LLR_02: Status Output Packaging • Format Return Payload: InterStatus proc_1->proc_2 Final Output Data out_sink Output Data Sinks & Status Return • data (UInt32) proc_2->out_sink Output Data & Status Code
Data Flow Diagram
Here is the call graph for this function:
memoryMap_Read32 Node1 memoryMap_Read32 Node1->Node1
Here is the caller graph for this function:
memoryMap_Read32 Node1 memoryMap_Read32 Node1->Node1 Node2 interDrv_Read32 Node1->Node2 Node2->Node2 Node3 core_cardInfo Node2->Node3 Node6 core_cardStatus Node2->Node6 Node9 core_getMemoryRegion Node2->Node9 Node10 readA429Reg Node2->Node10 Node47 readAnInReg Node2->Node47 Node61 readCoreReg Node2->Node61 Node66 readDiscreteInReg Node2->Node66 Node74 readDiscreteOutReg Node2->Node74 Node85 readPsuReg Node2->Node85 Node115 readPwmReg Node2->Node115 Node128 readRvdtReg Node2->Node128 Node3->Node3 Node4 modConfig_open Node3->Node4 Node5 modInfo_getBrdInfo Node3->Node5 Node4->Node4 Node5->Node5 Node6->Node6 Node7 modHsb_getMfbCbit Node6->Node7 Node8 modHsb_getMfbPbit Node6->Node8 Node7->Node7 Node8->Node8 Node9->Node4 Node9->Node9 Node10->Node10 Node11 a429_getCbit Node10->Node11 Node13 a429_getPbit Node10->Node13 Node15 a429_getTemp Node10->Node15 Node16 a429_rxDisableChannel Node10->Node16 Node22 a429_rxDisableParity Node10->Node22 Node23 a429_rxEnableParity Node10->Node23 Node25 a429_rxDisableSDIFilter Node10->Node25 Node26 a429_rxEnableChannel Node10->Node26 Node28 a429_rxGetState Node10->Node28 Node30 a429_rxSetSDIFilter Node10->Node30 Node32 a429_rxSetSpeed Node10->Node32 Node33 a429_txDisableChannel Node10->Node33 Node35 a429_txDisableParity Node10->Node35 Node37 a429_txEnableChannel Node10->Node37 Node39 a429_txEnableParity Node10->Node39 Node40 a429_txGetState Node10->Node40 Node42 a429_txSetSpeed Node10->Node42 Node43 readFIFOMsgs Node10->Node43 Node45 txBus Node10->Node45 Node11->Node11 Node13->Node13 Node15->Node15 Node16->Node16 Node22->Node22 Node22->Node23 Node23->Node23 Node25->Node25 Node26->Node26 Node28->Node28 Node30->Node30 Node32->Node32 Node33->Node33 Node35->Node35 Node37->Node37 Node39->Node39 Node40->Node40 Node42->Node42 Node43->Node43 Node45->Node45 Node47->Node47 Node48 analogIn_enableDisableCh Node47->Node48 Node52 analogIn_getAdcReading Node47->Node52 Node54 analogIn_getCbit Node47->Node54 Node56 analogIn_getChannelStatus Node47->Node56 Node57 analogIn_getInputRange Node47->Node57 Node58 analogIn_getPbit Node47->Node58 Node60 analogIn_getTemp Node47->Node60 Node48->Node48 Node52->Node52 Node54->Node54 Node56->Node56 Node57->Node57 Node58->Node58 Node60->Node60 Node61->Node61 Node62 core_getHeartbeatElapsed Count Node61->Node62 Node64 core_getHeartbeatResolution Node61->Node64 Node62->Node62 Node64->Node64 Node66->Node66 Node67 discreteIn_getCbit Node66->Node67 Node69 discreteIn_getChSense Node66->Node69 Node71 discreteIn_getPbit Node66->Node71 Node73 discreteIn_getTemp Node66->Node73 Node67->Node67 Node69->Node69 Node71->Node71 Node73->Node73 Node74->Node74 Node75 discreteOut_devicesConfig Node74->Node75 Node77 discreteOut_getCbit Node74->Node77 Node79 discreteOut_getPbit Node74->Node79 Node81 discreteOut_getTemp Node74->Node81 Node82 discreteOut_writeChState Node74->Node82 Node75->Node75 Node77->Node77 Node79->Node79 Node81->Node81 Node82->Node82 Node85->Node85 Node86 psu_getBoardTemp Node85->Node86 Node88 psu_getInputAmp Node85->Node88 Node90 psu_getInputVolt Node85->Node90 Node92 psu_getOutputRail12VAmp Node85->Node92 Node93 psu_getOutputRail12VTemp Node85->Node93 Node94 psu_getOutputRail12VVolt Node85->Node94 Node95 psu_getOutputRail3V3Amp Node85->Node95 Node96 psu_getOutputRail3V3AuxAmp Node85->Node96 Node97 psu_getOutputRail3V3AuxTemp Node85->Node97 Node98 psu_getOutputRail3V3AuxVolt Node85->Node98 Node99 psu_getOutputRail3V3Temp Node85->Node99 Node100 psu_getOutputRail3V3Volt Node85->Node100 Node101 psu_getOutputRail5VAmp Node85->Node101 Node102 psu_getOutputRail5VTemp Node85->Node102 Node103 psu_getOutputRail5VVolt Node85->Node103 Node104 psu_getOutputRailN12VAuxAmp Node85->Node104 Node105 psu_getOutputRailN12VAuxTemp Node85->Node105 Node106 psu_getOutputRailN12VAuxVolt Node85->Node106 Node107 psu_getOutputRailP12VAuxAmp Node85->Node107 Node108 psu_getOutputRailP12VAuxTemp Node85->Node108 Node109 psu_getOutputRailP12VAuxVolt Node85->Node109 Node110 psu_getPrimaryTransTemp Node85->Node110 Node111 psu_getPsuCbit Node85->Node111 Node113 psu_getPsuDiag Node85->Node113 Node86->Node86 Node88->Node88 Node90->Node90 Node92->Node92 Node93->Node93 Node94->Node94 Node95->Node95 Node96->Node96 Node97->Node97 Node98->Node98 Node99->Node99 Node100->Node100 Node101->Node101 Node102->Node102 Node103->Node103 Node104->Node104 Node105->Node105 Node106->Node106 Node107->Node107 Node108->Node108 Node109->Node109 Node110->Node110 Node111->Node111 Node113->Node113 Node115->Node115 Node116 pwm_disable Node115->Node116 Node119 pwm_enable Node115->Node119 Node121 pwm_getCbit Node115->Node121 Node123 pwm_getPbit Node115->Node123 Node125 pwm_getTemp Node115->Node125 Node126 pwm_setFrequencyDutycycle Node115->Node126 Node116->Node116 Node119->Node119 Node121->Node121 Node123->Node123 Node125->Node125 Node126->Node126 Node128->Node128 Node129 getSenseDemod1Demod2Data Node128->Node129 Node132 rvdt_configSec1 Node128->Node132 Node134 rvdt_configSec2 Node128->Node134 Node135 rvdt_getCbit Node128->Node135 Node137 rvdt_getPbit Node128->Node137 Node139 rvdt_getRefStatus Node128->Node139 Node143 rvdt_getSenseStatus Node128->Node143 Node146 rvdt_getTemp Node128->Node146 Node147 rvdt_initDev Node128->Node147 Node148 rvdt_setRefConfigCommand Node128->Node148 Node150 rvdt_setRefWaveEnable Node128->Node150 Node151 rvdt_setS1s2Config Node128->Node151 Node152 rvdt_setSenseConfigCommand Node128->Node152 Node153 rvdt_setSenseEnable Node128->Node153 Node154 rvdt_setSenseFilterCommand Node128->Node154 Node156 rvdt_setTestMux Node128->Node156 Node129->Node129 Node132->Node132 Node134->Node134 Node135->Node135 Node137->Node137 Node139->Node139 Node143->Node143 Node146->Node146 Node147->Node147 Node148->Node148 Node150->Node150 Node151->Node151 Node152->Node152 Node153->Node153 Node154->Node154 Node156->Node156

◆ memoryMap_Write32()

InterStatus memoryMap_Write32 ( const Address address,
const UInt32 data )

memoryMap_Write32.

Write 32-bit of data to the specified address.

Parameters
[in]addressThe address to which the data will be written.
[in]dataThe 32-bit data to write.
Returns
InterStatus - Interface status return code, If no error occurs during the operation of the function, it returns INTF_SUCCESS. Otherwise related error message is returned.
Return values
INTF_SUCCESS: Success.
ERR_MMAP_FAIL_TO_MAP: Unable to write to a certain register.

Low-Level Software Requirements (LLR)

Low-Level Requirement Specification: memoryMap_Write32

Requirement ID Parent HLR ID Detailed Low-Level Requirement Statement (EARS Format) Software Unit Reference Verification Method Status
LLR_MEMORYMAP_MEMORYMAP_WRITE32_01 HLR_IO_36773 WHEN memory address alignment validation fails ((address % 4) != 0), the memoryMap_Write32() function SHALL abort processing without performing memory write. memoryMap.c:memoryMap_Write32() Test Closed
LLR_MEMORYMAP_MEMORYMAP_WRITE32_02 HLR_IO_36773 WHEN memory address is 4-byte aligned, the memoryMap_Write32() function SHALL write 32-bit unsigned word data to volatile memory address address. memoryMap.c:memoryMap_Write32() Test Closed

Control Coupling Diagram (CCD)

ControlCouplingStructureChart Caller memoryMap_Write32() [Low-Level Device Drivers] Target endian32() [Low-Level Driver Helper] Caller:s->Target:n l_t0->l_b0   address (Flag) l_t1->l_b1   data (Flag) r_b0->r_t0   statusCode (InterStatus)
Control Coupling Structure Chart

Data Coupling Diagram (DCD)

DataCouplingStructureChart Caller memoryMap_Write32() [Low-Level Device Drivers] Target endian32() [Low-Level Driver Helper] Caller:s->Target:n l_t0->l_b0   address (Payload) l_t1->l_b1   data (Payload) r_b0->r_t0   stateTelemetry (Internal State)
Data Coupling Structure Chart

Control Flow Diagram (CFD)

cfd_memoryMap_Write32 start Entry: memoryMap_Write32() act_1 LLR_01: Action Step invoke routine `endian32()` to execute target subsystem hardware operation start->act_1 success_exit LLR_02: Final Exit return `the computed result` act_1->success_exit
Control Flow Diagram

Data Flow Diagram (DFD)

dfd_memoryMap_Write32 in_store Input Data Sources & Parameters • address (const Address) • data (const UInt32) proc_1 LLR_01: Data Payload Transformation • Process payload via endian32() in_store->proc_1 Data Payload (endian32) proc_2 LLR_02: Status Output Packaging • Format Return Payload: InterStatus proc_1->proc_2 Final Output Data out_sink Output Data Sinks & Status Return • Status Payload (InterStatus) proc_2->out_sink Output Data & Status Code
Data Flow Diagram
Here is the call graph for this function:
memoryMap_Write32 Node1 memoryMap_Write32 Node1->Node1
Here is the caller graph for this function:
memoryMap_Write32 Node1 memoryMap_Write32 Node1->Node1 Node2 interDrv_Write32 Node1->Node2 Node2->Node2 Node3 writeA429Reg Node2->Node3 Node39 writeAnInReg Node2->Node39 Node44 writeCoreReg Node2->Node44 Node52 writeDiscreteOutReg Node2->Node52 Node59 writePwmReg Node2->Node59 Node67 writeRvdtReg Node2->Node67 Node3->Node3 Node4 a429_configMCR Node3->Node4 Node9 a429_reset Node3->Node9 Node10 a429_rxDisableChannel Node3->Node10 Node12 a429_rxDisableParity Node3->Node12 Node13 a429_rxEnableParity Node3->Node13 Node15 a429_rxDisableSDIFilter Node3->Node15 Node16 a429_rxEnableChannel Node3->Node16 Node18 a429_rxSetSDIFilter Node3->Node18 Node20 a429_rxSetSpeed Node3->Node20 Node21 a429_txDisableChannel Node3->Node21 Node23 a429_txDisableParity Node3->Node23 Node25 a429_txEnableChannel Node3->Node25 Node27 a429_txEnableParity Node3->Node27 Node28 a429_txSetSpeed Node3->Node28 Node29 configLabelFilter Node3->Node29 Node33 readFIFOMsgs Node3->Node33 Node36 txBus Node3->Node36 Node4->Node4 Node5 modA429_initReset Node4->Node5 Node5->Node5 Node6 modConfig_init Node5->Node6 Node7 modConfig_reset Node5->Node7 Node6->Node6 Node7->Node7 Node8 modConfig_close Node7->Node8 Node8->Node8 Node9->Node5 Node9->Node9 Node10->Node10 Node11 modA429_recvChDisable Node10->Node11 Node11->Node5 Node11->Node11 Node12->Node11 Node12->Node12 Node12->Node13 Node14 modA429_recvConfig Node12->Node14 Node13->Node13 Node13->Node14 Node14->Node14 Node15->Node11 Node15->Node15 Node16->Node16 Node17 modA429_recvChEnable Node16->Node17 Node17->Node17 Node18->Node18 Node19 modA429_recvSetSDIFilter Node18->Node19 Node19->Node19 Node20->Node14 Node20->Node20 Node21->Node21 Node22 modA429_sendChDisable Node21->Node22 Node22->Node5 Node22->Node22 Node23->Node22 Node23->Node23 Node24 modA429_sendConfig Node23->Node24 Node24->Node24 Node25->Node25 Node26 modA429_sendChEnable Node25->Node26 Node26->Node26 Node27->Node24 Node27->Node27 Node28->Node24 Node28->Node28 Node29->Node29 Node30 a429_rxClearLabelFilter Node29->Node30 Node31 a429_rxSetLabelFilter Node29->Node31 Node30->Node11 Node30->Node30 Node31->Node31 Node32 modA429_recvSetLabelFilter Node31->Node32 Node32->Node32 Node33->Node33 Node34 a429_rxGetFIFOMsgs Node33->Node34 Node34->Node34 Node35 modA429_recvFIFO Node34->Node35 Node35->Node35 Node36->Node36 Node37 a429_txFIFOMsg Node36->Node37 Node37->Node37 Node38 modA429_send Node37->Node38 Node38->Node38 Node39->Node39 Node40 analogIn_enableDisableCh Node39->Node40 Node40->Node40 Node41 modAnalogIn_disableRead Node40->Node41 Node43 modAnalogIn_enableRead Node40->Node43 Node41->Node41 Node42 modAnalogIn_initReset Node41->Node42 Node42->Node6 Node42->Node7 Node42->Node42 Node43->Node43 Node44->Node44 Node45 core_enableDisableHeartbeat Node44->Node45 Node48 core_feedHeartbeat Node44->Node48 Node50 core_setHeartbeatTimeout Count Node44->Node50 Node45->Node45 Node46 modHeartbeat_disableHeartbeat Node45->Node46 Node47 modHeartbeat_enableHeartbeat Node45->Node47 Node46->Node8 Node46->Node46 Node47->Node47 Node48->Node48 Node49 modHeartbeat_feedHeartbeat Node48->Node49 Node49->Node49 Node50->Node50 Node51 modHeartbeat_setTimeout Node50->Node51 Node51->Node51 Node52->Node52 Node53 discreteOut_devicesConfig Node52->Node53 Node55 discreteOut_reset Node52->Node55 Node57 discreteOut_writeChState Node52->Node57 Node53->Node53 Node54 modDiscreteOut_devicesConfig Node53->Node54 Node54->Node54 Node55->Node55 Node56 modDiscreteOut_initReset Node55->Node56 Node56->Node6 Node56->Node7 Node56->Node56 Node57->Node57 Node58 modDiscreteOut_write Node57->Node58 Node58->Node56 Node58->Node58 Node59->Node59 Node60 pwm_disable Node59->Node60 Node63 pwm_enable Node59->Node63 Node65 pwm_setFrequencyDutycycle Node59->Node65 Node60->Node60 Node61 modPwm_disable Node60->Node61 Node61->Node61 Node62 modPwm_initReset Node61->Node62 Node62->Node6 Node62->Node7 Node62->Node62 Node63->Node63 Node64 modPwm_enable Node63->Node64 Node64->Node64 Node65->Node65 Node66 modPwm_setFrequencyDutycycle Node65->Node66 Node66->Node66 Node67->Node67 Node68 configSec1BpfA2 Node67->Node68 Node71 configSec1BpfA3 Node67->Node71 Node72 configSec1BpfB1 Node67->Node72 Node73 configSec1Lpf Node67->Node73 Node75 configSec2BpfA2 Node67->Node75 Node76 configSec2BpfA3 Node67->Node76 Node77 configSec2BpfB1 Node67->Node77 Node78 configSec2Lpf Node67->Node78 Node79 rvdt_configSec1 Node67->Node79 Node81 rvdt_configSec2 Node67->Node81 Node82 rvdt_configWaveformGeneration Node67->Node82 Node84 rvdt_initDev Node67->Node84 Node86 rvdt_setPowerEnable Node67->Node86 Node89 rvdt_setRefConfigCommand Node67->Node89 Node90 rvdt_setRefWaveEnable Node67->Node90 Node93 rvdt_setS1s2Config Node67->Node93 Node94 rvdt_setSenseConfigCommand Node67->Node94 Node95 rvdt_setSenseEnable Node67->Node95 Node96 rvdt_setSenseFilterCommand Node67->Node96 Node97 rvdt_setTestMux Node67->Node97 Node68->Node68 Node69 rvdt_configBpfCoefficient Node68->Node69 Node69->Node69 Node70 modRvdt_SetSenseFilter Node69->Node70 Node70->Node70 Node71->Node69 Node71->Node71 Node72->Node69 Node72->Node72 Node73->Node73 Node74 rvdt_configLpfCoefficient Node73->Node74 Node74->Node70 Node74->Node74 Node75->Node69 Node75->Node75 Node76->Node69 Node76->Node76 Node77->Node69 Node77->Node77 Node78->Node74 Node78->Node78 Node79->Node79 Node80 modRvdt_SetSenseConfig Node79->Node80 Node80->Node80 Node81->Node80 Node81->Node81 Node82->Node82 Node83 modRvdt_SetRefConfig Node82->Node83 Node83->Node83 Node84->Node84 Node85 modRvdt_initReset Node84->Node85 Node85->Node6 Node85->Node7 Node85->Node85 Node86->Node86 Node87 modRvdt_SenseDisable Node86->Node87 Node88 modRvdt_SenseEnable Node86->Node88 Node87->Node85 Node87->Node87 Node88->Node88 Node89->Node83 Node89->Node89 Node90->Node90 Node91 modRvdt_RefDisable Node90->Node91 Node92 modRvdt_RefEnable Node90->Node92 Node91->Node85 Node91->Node91 Node92->Node92 Node93->Node80 Node93->Node93 Node94->Node80 Node94->Node94 Node95->Node87 Node95->Node88 Node95->Node95 Node96->Node70 Node96->Node96 Node97->Node80 Node97->Node97